adav802 Analog Devices, Inc., adav802 Datasheet - Page 18

• Manufacturer Part Number: adav802
• Description: Audio Codec For Recordable Dvd
• Manufacturer: Analog Devices, Inc.

ADAV802
is 16 samples. However, the Group Delay and Mute In register
can be used to increase this offset. The number of input samples
added to the write pointer of the FIFO on the SRC is 16 + Bits
6-0 of the Group Delay register. This feature is useful in vari-
speed applications in order to prevent the read pointer to the
FIFO running ahead of the write pointer. When set, bit 7 of the
Group Delay and Mute In register will soft mute the sample
rate. Increasing the offset of the write address pointer is useful
for applications when small changes in the sample rate ratio
between f
rate can be calculated from the RAM word depth and the group
delay as (512−16)/64 taps = 7.75 for short group delay and (512-
64)/64 taps = 7 for long group delay.
The digital servo loop is essentially a ramp filter that provides
the initial pointer to the address in RAM and ROM for the start
of the FIR convolution. The RAM pointer is the integer output
of the ramp filter while the ROM is the fractional part. The
digital servo loop must be able to provide excellent rejection of
jitter on the f
of the f
divide the fractional part of the ramp output by the ratio of
f
the ROM coefficients.
The digital servo loop is implemented with a multi-rate filter. To
settle the digital servo loop filter more quickly upon startup or a
change in the sample rate, a “fast mode” was added to the filter.
When the digital servo loop starts up or the sample rate is
changed, the digital servo loop kicks into “fast mode” to adjust
and settle on the new sample rate. Upon sensing the digital
servo loop settling down to some reasonable value, the digital
servo loop will kick into “normal” or “slow mode. ”
During “fast mode” the MUTE_OUT bit in the Sample Rate
Error register is asserted to let the user know clicks or pops may
be present in the digital audio data. The output of the SRC can
be muted, by asserting bit 7 of the Group Delay & Mute register
until the SRC has changed to “slow mode”. The MUTE_OUT bit
can be set to generate an interrupt when the SRC changes to
“slow mode” indicating that the data will be sample rate
converted accurately. The frequency response of the digital
servo loop for "fast mode" and "slow mode" are shown in Figure
14. The FIR filter is a 64-tap filter in the case of f
is (f
filter performs its convolution by loading in the starting address
of the RAM address pointer and the ROM address pointer from
the digital servo loop at the start of the f
filter then steps through the RAM by decrementing its address
by 1 for each tap, and the ROM pointer increments its address
by the (f
f
completed. The convolution is performed for both the left and
right channels, and the multiply accumulate circuit used for the
convolution is shared between the channels. The f
S_IN
S_IN
/f
S_IN
. Once the ROM address rolls over, the convolution is
S_OUT
/f
S_OUT
S_OUT
S_OU
S_IN
for the case when f
T/f
clock within 4.97 ps. The digital servo loop will also
) × 64 taps for the case when f
S_IN
and f
S_IN
and f
) × 2
S_OUT
S_OUT
20
are expected. The maximum decimation
ratio for f
clocks as well as measure the arrival
S_IN
> f
S_IN
S_OUT
> f
, to dynamically alter
S_OUT
S_OUT
S_IN
period. The FIR
or 2
> f
S_OUT
S_OUT
20
S_IN
for f
/f
≥ f
. The FIR
S_OUT
S_OUT
S_IN
Rev. Pr G | Page 18 of 53
and
≥
sample rate ratio circuit is used to dynamically alter the
coefficients in the ROM for the case when f
is calculated by comparing the output of an f
output of an f
If f
by more than two f
comparison. This is done to provide some hysteresis to prevent
the filter length from oscillating and causing distortion.
PLL SECTION
The ADAV802 features a dual PLL configuration to generate
independent system clocks for asynchronous operation. Figure
17 shows the block diagram of the PLL section. The PLL
generates the internal and system clocks from a 27MHz clock.
This clock is generated either by a crystal connected between
XIN and XOUT, as shown in Figure 15 or from an external
Figure 14. Frequency Response of the Digital Servo Loop. fS_IN is the X-Axis,
S_IN
> f
S_OUT
REG: 0x76
BIT 1
Figure 13. Clock and Data Path Control on the SRC
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
-200
-210
-220
-10
-20
-30
-40
-50
-60
-70
-80
-90
10
0.01
0
S_IN
, the sample rate ratio is updated if it is different
fS_OUT = 192 KHz, Master Clock is 30 MHz
counter. If f
S_OUT
0.1
OUTPUT
MCLK
SRC
Preliminary Technical Data
SRC
SRC
periods from the previous f
1
FREQUENCY - Hz
SLOW MODE
INPUT
S_OUT
SRC
REG: 0x00
BITS 1-0
10
REG: 0x76
BIT 0
>f
REG: 0x62
BITS 7-6
100
S_IN,
FAST MODE
the ratio is held at one.
1e3
S_IN
AUXILIARY IN
PLAYBACK
DIR
ADC
S_OUT
>f
1e4
S_OUT
counter to the
S_OUT
1e5
. The ratio
to f
S_IN