adav802 Analog Devices, Inc., adav802 Datasheet - Page 19

• Manufacturer Part Number: adav802
• Description: Audio Codec For Recordable Dvd
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
clock source connected directly to XIN. A 54MHz clock can
also be used if the internal clock divider is used. Both PLLs
(PLL1 and PLL2) can be programmed independently and cater
for a range of sampling rates (32/44.1/48 kHz) with selectable
system clock oversampling rates of 256 and 384. Higher
oversampling rates can also be selected by enabling the
doubling of the sampling rate to give 512 or 768 × f
that this option also allows oversampling ratios of 256 or 384 at
double sample rates of 64/88.2/96 kHz. The PLL outputs can be
routed internally to act as clock sources for the other
component blocks such as the ADC, DAC etc. The outputs of
the PLLs are also available on the three SYSCLK pins. Figure 18
shows how the PLLs can be configured to provide the sampling
clocks.
Figure 15. Crystal Connection
MCLKO
MCLKI
XOUT
C
XIN
801-0015
XTAL
REG: 0x74
BIT 5
C
/2
REG: 0x74
BIT 4
/2
S
ratios. Note
Figure 17. PLL Section Block Diagram
REG: 0x78
REG: 0x78
Rev. Pr G | Page 19 of 53
BIT 7
BIT 6
DETECTOR
DETECTOR
& LOOP
& LOOP
PHASE
FILTER
PHASE
FILTER
PLL_LF2
Table 19. PLL Frequency Selection Options
PLL
1
2A
2B
The PLLs require a some external components to operate
correctly. These components, shown in Figure 16 form a loop
filter which integrates the current pulses from a charge pump
and produces a voltage which is used to tune the VCO. Good
quality capacitors, such as PPS film, are recommended .Figure
17 shows a block diagram of the PLL section including master
clock selection. Figure 18 shows how the clock frequencies at
the clock output pins, SYSCLK1-3 and the internal PLL clock
values, PLL1 and PLL2 are selected. The clock nodes, PLL1 and
PLL2, can be used as master clocks for the other blocks in the
ADAV802 such as the DAC or ADC. The PLL has separate
supply and ground pins and these should be as clean as possible
to prevent electrical noise being converted into clock jitter by
coupling onto the loop filter pins.
PLL_LF1
N DIVIDER
N DIVIDER
VCO
VCO
Sample Rate
(f
32/44.1/48 kHz
64/88.2/96 kHz
32/44.1/48 kHz
64/88.2/96 kHz
Same as f
for PLL 2A
S
)
1.8nF
S
AVDD
selected
SCALER N2
SCALER N3
SCALER N1
OUTPUT
OUTPUT
OUTPUT
732Ω
33nF
Figure 16. PLL L
PLL1
PLL2
MCLK Selection
Normal f
256/384×f
256/384×f
512×f
512×f
F
PLL_LFx
SYSCLK1
SYSCLK2
SYSCLK3
BLOCK
S
S
PLL
S
S
S
ADAV802
Double f
512/768×f
256/384×f
512/768×f
256/384×f
S
S
S
S
S