lan9311 Standard Microsystems Corp., lan9311 Datasheet - Page 157

• Manufacturer Part Number: lan9311
• Description: Lan9311/lan9311i Two Port 10/100 Managed Ethernet Switch With 16-bit Non-pci Cpu Interface
• Manufacturer: Standard Microsystems Corp.

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i
11.2
IEEE 1588 CLOCK MODE
0
The LAN9311/LAN9311i contains three identical IEEE 1588 Time Stamp blocks as shown in
Figure
64-bit IEEE 1588 clock time upon detection of a Sync or Delay_Req message type on their respective
port. The mode of the clock (master or slave) determines which message is detected on receive and
transmit. For slave clock operation, Sync messages are detected on receive and Delay_Req messages
on transmit. For master clock operation, Delay_Req messages are detected on receive and Sync
messages on transmit. Follow_Up, Delay_Resp and Management packet types do not cause capture.
Each port may be individually configured as an IEEE 1588 master or slave clock via the master/slave
bits (M_nS_1 for Port 1, MnS_2 for Port2, and M_nS_MII for Port 0) in the
(1588_CONFIG).
1588 clock operation.
For ports 1 and 2, receive is defined as data from the PHY (from the outside world) and transmit is
defined as data to the PHY. This is consistent with the point-of-view of where the partner clock resides
(LAN9311/LAN9311i receives packets from the partner via the PHY, etc.). For the time stamp module
connected to the Host MAC (Port 0), the definition of transmit and receive is reversed. Receive is
defined as data from the switch fabric, while transmit is defined as data to the switch fabric. This is
consistent with the point-of-view of where the partner clock resides (LAN9311/LAN9311i receives
packets from the partner via the switch fabric, etc.).
As defined by IEEE 1588, and shown in
leading edge of the first data bit following the Start of Frame Delimiter (SFD). However, since the
packet contents are not yet known, the time stamp can not yet be loaded into the capture register.
Therefore, the time stamp is first stored into a temporary internal holding register at the start of every
packet.
IEEE 1588 Time Stamp
Preamble
(M_nS_x = 0)
(M_nS_x = 1)
1
Octet
Master
Slave
0
11.1. These blocks are responsible for capturing the source UUID, sequence ID, and current
1
0
Figure 11.2 IEEE 1588 Message Time Stamp Point
Table 11.1
1
Table 11.1 IEEE 1588 Message Type Detection
0
1
summarizes the message type detection under slave and master IEEE
Start of Frame
Message Timestamp
Delimiter
Ethernet
0
DATASHEET
1
Point
bit time
0
Figure
157
Delay_Req
RECEIVE
1 1 1
Sync
11.2, the message time stamp point is defined as the
0 0 0 0 0 0 0
0 0 0 0 0 0
Start of Frame
First Octet
following
1588 Configuration Register
TRANSMIT
Delay_Req
Revision 1.2 (04-08-08)
Sync