lan9311 Standard Microsystems Corp., lan9311 Datasheet - Page 265

• Manufacturer Part Number: lan9311
• Description: Lan9311/lan9311i Two Port 10/100 Managed Ethernet Switch With 16-bit Non-pci Cpu Interface
• Manufacturer: Standard Microsystems Corp.

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i
14.2.9.4
31:18
13:11
BITS
17
16
15
14
10
RESERVED
Energy-Detect Status Port 2 (ED_STS2)
This bit indicates an energy detect event occurred on the Port 2 PHY.
In order to clear this bit, it is required that the event in the PHY be cleared
as well. The event sources are described in
Management," on page
Energy-Detect Status Port 1 (ED_STS1)
This bit indicates an energy detect event occurred on the Port 1 PHY.
In order to clear this bit, it is required that the event in the PHY be cleared
as well. The event sources are described in
Management," on page
Energy-Detect Enable Port 2 (ED_EN2)
When set, the PME signal (if enabled via the PME_EN bit) will be asserted
in accordance with the PME_IND bit upon an energy-detect event from Port
2. When set, the PME_INT bit in the
also be asserted upon an energy-detect event from Port 2, regardless of the
setting of the PME_EN bit.
Note:
Energy-Detect Enable Port 1 (ED_EN1)
When set, the PME signal (if enabled via the PME_EN bit) will be asserted
in accordance with the PME_IND bit upon an energy-detect event from Port
1. When set, the PME_INT bit in the
also be asserted upon an energy-detect event from Port 1, regardless of the
setting of the PME_EN bit.
Note:
RESERVED
Virtual PHY Reset (VPHY_RST)
Writing a 1 to this bit resets the Virtual PHY. When the Virtual PHY is
released from reset, this bit is automatically cleared. All writes to this bit are
ignored while this bit is high.
Power Management Control Register (PMT_CTRL)
This read-write register controls the power management features and the PME pin of the
LAN9311/LAN9311i. The ready state of the LAN9311/LAN9311i can be determined via the Device
Ready (READY) bit of this register. Refer to
additional information.
Note: This register is one of only four registers (the others are HW_CFG, BYTE_TEST, and
Note: Either half of this register can be read without the need to read the other half.
The EDPWRDOWN bit of the
Register (PHY_MODE_CONTROL_STATUS_x)
must also be set to enable the energy detect feature.
The EDPWRDOWN bit in the
Register (PHY_MODE_CONTROL_STATUS_x)
must also be set to enable the energy detect feature.
RESET_CTL) which can be polled while the LAN9311/LAN9311i is in the reset or not ready
state (READY bit is cleared).
Offset:
46.
46.
084h
DESCRIPTION
Interrupt Status Register (INT_STS)
Interrupt Status Register (INT_STS)
DATASHEET
Port x PHY Mode Control/Status
Port x PHY Mode Control/Status
Section 4.3, "Power
Section 4.3, "Power
265
Size:
Section 4.3, "Power Management," on page 46
of the Port 2 PHY
of the Port 1 PHY
32 bits
will
will
R/WC
R/WC
TYPE
R/W
R/W
R/W
RO
RO
SC
Revision 1.2 (04-08-08)
DEFAULT
0b
0b
0b
0b
0b
-
-
for