lan9311 Standard Microsystems Corp., lan9311 Datasheet - Page 452

• Manufacturer Part Number: lan9311
• Description: Lan9311/lan9311i Two Port 10/100 Managed Ethernet Switch With 16-bit Non-pci Cpu Interface
• Manufacturer: Standard Microsystems Corp.

Revision 1.2 (04-08-08)
15.5.7
SYMBOL
FIFO_SEL
END_SEL
nCS, nRD
t
t
t
t
t
t
t
t
csdv
acyc
t
asu
adv
don
doff
doh
csh
D[15:0]
ah
A[2:1]
RX Data FIFO Direct PIO Burst Read Cycle Timing
Please refer to
description of this mode.
Note: A RX Data FIFO direct PIO burst read cycle begins when both nCS and nRD are asserted.
Note: A[1] must toggle, fresh data is supplied each time A[1] toggles.
nCS, nRD De-assertion Time
nCS, nRD Valid to Data Valid
Address Cycle Time
Address, FIFO_SEL Setup to nCS, nRD Valid
Address Stable to Data Valid
Address, FIFO_SEL Hold Time
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
Table 15.11 RX Data FIFO Direct PIO Burst Read Cycle Timing Values
The cycle ends when either or both nCS and nRD are de-asserted. They may be asserted and
de-asserted in any order.
Figure 15.7 RX Data FIFO Direct PIO Burst Read Cycle Timing
t
asu
Section 8.5.7, "RX Data FIFO Direct PIO Burst Reads," on page 110
t
don
t
acyc
t
csdv
DESCRIPTION
DATASHEET
t
adv
t
acyc
452
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
t
adv
MIN
13
45
0
0
0
0
t
adv
t
acyc
t
ah
TYP
SMSC LAN9311/LAN9311i
t
doh
t
doff
MAX
t
csh
30
40
9
for a functional
Datasheet
UNITS
nS
nS
nS
nS
nS
nS
nS
nS
nS