lan9311 Standard Microsystems Corp., lan9311 Datasheet - Page 22

• Manufacturer Part Number: lan9311
• Description: Lan9311/lan9311i Two Port 10/100 Managed Ethernet Switch With 16-bit Non-pci Cpu Interface
• Manufacturer: Standard Microsystems Corp.

Revision 1.2 (04-08-08)
2.2.1
2.2.2
System Clocks/Reset/PME Controller
A clock module contained within the LAN9311/LAN9311i generates all the system clocks required by
the device. This module interfaces directly with the external 25MHz crystal/oscillator to generate the
required clock divisions for each internal module, with the exception of the 1588 clocks, which are
generated in the 1588 Time Stamp Clock/Events module. A 16-bit general purpose timer and 32-bit
free-running clock are provided by this module for general purpose use.
The LAN9311/LAN9311i reset events are categorized as chip-level resets, multi-module resets, and
single-module resets.
A chip-level reset is initiated by assertion of any of the following input events:
A multi-module reset is initiated by assertion of the following:
A single-module reset is initiated by assertion of the following:
The LAN9311/LAN9311i supports numerous power management and wakeup features. The Port 1 &
2 PHYs provide general power-down and energy detect power-down modes, which allow a reduction
in PHY power consumption. The Host MAC provides wake-up frame detection and magic packet
detection modes. The LAN9311/LAN9311i can be programmed to issue an external wake signal (PME)
via several methods, including wake on LAN, wake on link status change (energy detect), and magic
packet wakeup. The PME signal is ideal for triggering system power-up using remote Ethernet wakeup
events.
System Interrupt Controller
The LAN9311/LAN9311i provides a multi-tier programmable interrupt structure which is controlled by
the System Interrupt Controller. At the top level are the
Interrupt Enable Register
various LAN9311/LAN9311i sub-modules. The LAN9311/LAN9311i is capable of generating interrupt
events from the following:
Power-On Reset
nRST Pin Reset
Digital Reset - DIGITAL_RST (bit 0) in the
and Virtual PHY)
Soft Reset - SRST (bit 0) in the
Port 2 PHY Reset - PHY2_RST (bit 2) in the
15) in the
Port 1 PHY Reset - PHY1_RST (bit 1) in the
15) in the
Virtual PHY Reset - VPHY_RST (bit 0) in the
the
Control Register (VPHY_BASIC_CTRL)
1588 Time Stamp
Switch Fabric
Ethernet PHYs
GPIOs
Host MAC (FIFOs, power management)
- Resets all LAN9311/LAN9311i sub-modules except the Ethernet PHYs (Port 1 PHY, Port 2 PHY,
- Resets the HBI, Host MAC, and System CSRs below address 100h
- Resets the Port 2 PHY
- Resets the Port 1 PHY
- Resets the Virtual PHY
Power Management Control Register
Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x)
Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x)
(INT_EN). These registers aggregate and control all interrupts from the
DATASHEET
Hardware Configuration Register (HW_CFG)
22
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
(PMT_CTRL), or Reset (bit 15) in the
Reset Control Register (RESET_CTL)
Reset Control Register (RESET_CTL)
Reset Control Register (RESET_CTL)
Reset Control Register
Interrupt Status Register (INT_STS)
(RESET_CTL), (bit 10) in
SMSC LAN9311/LAN9311i
Virtual PHY Basic
or Reset (bit
or Reset (bit
Datasheet
and