lan9311 Standard Microsystems Corp., lan9311 Datasheet - Page 165

• Manufacturer Part Number: lan9311
• Description: Lan9311/lan9311i Two Port 10/100 Managed Ethernet Switch With 16-bit Non-pci Cpu Interface
• Manufacturer: Standard Microsystems Corp.

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i
13.2.2.2
13.3
nP2LED3
nP2LED2
nP2LED1
nP2LED0
nP1LED3
nP1LED2
(GPIO7)
(GPIO6)
(GPIO5)
(GPIO4)
(GPIO3)
(GPIO2)
GPIO_INT_POL[9:8] bits also determine the polarity of the clock events as described in
Section
IEEE 1588 GPIO Interrupts
In addition to the standard GPIO interrupts in the
Register
to generate and clear specific IEEE 1588 related interrupts. When GPIO 9 or GPIO 8 are enabled as
inputs and an active edge occurs, the IEEE 1588 clock capture is indicated by the 1588_GPIO9_INT
and 1588_GPIO8_INT interrupts respectively in the
(1588_INT_STS_EN). These interrupts are enabled by setting the corresponding 1588_GPIO9_EN
and 1588_GPIO8_EN bits in the
GPIO inputs must be active for greater than 40nS to be recognized as capture events.
When GPIO 8 and GPIO 9 are enabled, the 1588 Timer Interrupt bit (1588_TIMER_INT) of the
Interrupt Status and Enable Register (1588_INT_STS_EN)
GPIO[9:8]. A clear is only registered when the GPIO input is active for greater than 40nS.
Eight pins, GPIO[7:0], are shared with LED functions (nP1LED[3:0] and nP2LED[3:0]). These pins are
configured as LED outputs by setting the corresponding LED_EN bit in the
(LED_CFG). When configured as a LED, the pin is an open-drain, active-low output and the GPIO
related input buffer and pull-up are disabled. The LED outputs are always active low. As a result, a
low signal on the LED pin equates to the LED “on”, and a high signal equates to the LED “off”.
The functions associated with each LED pin are configurable via the LED_FUN[1:0] bits of the
Configuration Register
various port related functions. These functions are described in
definition of each indication type.
The default values of the LED_FUN[1:0] and LED_EN[7:0] bits of the
(LED_CFG)
For more information on the
Section 14.2.3.4, "LED Configuration Register (LED_CFG)," on page
LED Operation
Full-duplex / Collision
Link / Activity
Link / Activity
13.2.1.2.
(GPIO_INT_STS_EN), the IEEE 1588 timestamp enabled GPIO[9:8] pins contain the ability
Speed
Port 0
Port 2
Port 2
Port 2
Port 0
Port 1
are determined by the LED_fun_strap[1:0] and LED_en_strap[7:0] configuration straps.
00b
RX
TX
Table 13.1 LED Operation as a Function of LED_CFG[9:8]
(LED_CFG). These bits allow the configuration of each LED pin to indicate
Full-duplex / Collision
LED Configuration Register (LED_CFG)
100Link / Activity
100Link / Activity
10Link / Activity
1588 Interrupt Status and Enable Register
DATASHEET
LED_CFG[9:8] (LED_FUN[1:0])
Port 0
Port 2
Port 2
Port 2
Port 0
Port 1
01b
RX
TX
165
General Purpose I/O Interrupt Status and Enable
Full-duplex / Collision
1588 Interrupt Status and Enable Register
Activity
Activity
Speed
Port 2
Port 2
Port 2
Port 2
Port 1
Port 1
can be cleared by an active edge on
Link
Link
10b
Table 13.1
197.
and its related straps, refer to
LED Configuration Register
LED Configuration Register
followed by a detailed
(1588_INT_STS_EN).
Revision 1.2 (04-08-08)
Port 2
RXDV
Port 2
Port 0
RXDV
Port 0
TXEN
TXEN
11b
-
-
1588
LED