peb20532 Infineon Technologies Corporation, peb20532 Datasheet - Page 143

• Manufacturer Part Number: peb20532
• Description: 2 Channel Serial Optimized Communication Controller
• Manufacturer: Infineon Technologies Corporation

Data Sheet
XDOV
XFW
CTS
RFNE
CD
Transmit FIFO Data Overflow
XDOV=’0’
XDOV=’1’
Transmit FIFO Write Enable
XFW=’0’
XFW=’1’
CTS (Clear To Send) Input Signal State
CTS=’0’
CTS=’1’
Note: A transmit clock is necessary to detect the input level of CTS.
Receive FIFO Not Empty
This status bit is set if the SCC receive FIFO (RFIFO) holds at least one
valid byte.
RFNE=’0’
RFNE=’1’
CD (Carrier Detect) Input Signal State
This status bit gives the signal state of CD input. This bit value is
independent of the programmed polarity of the Carrier Detect function
(bit ’ICD’ in register
CD=’0’
CD=’1’
Note: Optionally this input can be programmed to generate an interrupt
Optionally this input can be programmed to generate an interrupt
on signal level changes.
on signal level changes.
Less than or equal to 32 bytes have been written to the
XFIFO.
More than 32 bytes have been written to the XFIFO. This
bit is reset by:
– a transmitter reset command ’XRES’
– or when all bytes in the accessible half of the XFIFO
The XFIFO is not able to accept further transmit data.
Transmit data can be written to the XFIFO.
CTS input signal is inactive (high level)
CTS input signal is active (low level)
The receive FIFO is empty.
The receive FIFO is not empty.
CD input signal is low.
CD input signal is high.
have been moved into the inaccessible half.
CCR1H
5-143
).
Register Description (STARH)
(async/bisync modes)
PEB 20532
PEF 20532
(all modes)
(all modes)
(all modes)
(all modes)
2000-09-14