peb20532 Infineon Technologies Corporation, peb20532 Datasheet - Page 168

• Manufacturer Part Number: peb20532
• Description: 2 Channel Serial Optimized Communication Controller
• Manufacturer: Infineon Technologies Corporation

Data Sheet
ELC
TCDE
AFX
Enable Length Check
This bit is only valid in HDLC SS7 mode:
If the number of received octets exceeds 272 + 7 within one Signaling
Unit, reception is aborted and bit RSTA.RAB is set.
ELC=’0’
ELC=’1’
Termination Character Detection Enable
This bit is valid in ASYNC/BISYNC modes only and enables/disables the
termination character detection mechanism:
TCDE = ’0’
TCDE = ’1’
Automatic FISU Transmission
This bit is only valid in HDLC SS7 mode:
After the contents of the transmit FIFO (XFIFO) has been transmitted
completely, FISUs are transmited automatically. These FISUs contain
the FSN and BSN of the last transmitted Signaling Unit (provided in
XFIFO).
AFX=’0’
AFX=’1’
Length Check disabled.
Length Check enabled.
No receive termination character detection is performed.
The termination character detection is enabled. The
receive data stream is monitored for the occurence of a
termination character (TC) programmed via register TCR.
When this character is detected, a ’TCD’ interrupt is
generated to the CPU (unless masked).
Note: If the programmed character length (bit field
Automatic FISU transmission disabled.
Automatic FISU transmission enabled.
’CHL(1:0)’) is less than 8 bits, the most significant
unused bits in register
Otherwise
detected.
5-168
no
termination
Register Description (CCR3H)
TCR
(async/bisync modes)
must be set to ’0’.
character
PEB 20532
PEF 20532
(hdlc mode)
(hdlc mode)
2000-09-14
will
be