peb20532 Infineon Technologies Corporation, peb20532 Datasheet - Page 83

• Manufacturer Part Number: peb20532
• Description: 2 Channel Serial Optimized Communication Controller
• Manufacturer: Infineon Technologies Corporation

4.1
The HDLC controller of each serial channel (SCC) can be programmed to operate in
various modes, which are different in the treatment of the HDLC frame in receive
direction. Thus, the receive data flow and the address recognition features can be
performed in a very flexible way satisfying almost any application specific requirements.
There are 4 different HDLC operating modes which can be selected via register bits
CCR2L:MDS[1:0] and CCR2L:ADM.
4.1.1
The following table provides an overview of the different address comparison
mechanisms in HDLC operating modes:
Table 13
Mode
4.1.1.1
Characteristics: Window size 1, random message length, address recognition.
The SCC processes autonomously all numbered frames (S-, I-frames) of an HDLC
protocol. The HDLC control field, I-field data of the frames and an additional status byte
are temporarily stored in the SCC receive FIFO.
Data Sheet
Address
Address
Address
Mode 2
Mode 1
Mode 0
Mode
Auto
-
HDLC/SDLC Protocol Modes
HDLC Submodes Overview
Automode
Address
Field
16 bit
8 bit
8 bit
None
Address Comparison Overview
FE
FE
FE
H
H
H
High Address Byte
/ FC
/ FC
/ FC
don’t care
H
H
H
Recognized Address Bytes for a Match:
(1111 11 C/R 0
(1111 11 C/R 0
(1111 11 C/R 0
RAH1
RAH1
RAH2
RAH2
RAH1
RAH2
RAL1
RAL2
83
2
2
2
)
)
)
and
and
and
and
and
and
Detailed Protocol Description
Low Address Byte
don’t care
don’t care
don’t care
don’t care
don’t care
don’t care
RAL1
RAL2
RAL1
RAL2
RAL1
RAL2
PEB 20532
PEF 20532
2000-09-14