peb20532 Infineon Technologies Corporation, peb20532 Datasheet - Page 157

• Manufacturer Part Number: peb20532
• Description: 2 Channel Serial Optimized Communication Controller
• Manufacturer: Infineon Technologies Corporation

Data Sheet
DIV
ODS
ICD
RTS
Data Inversion
This bit is only valid if NRZ data encoding is selected via bit field SC(2:0)
in register CCR0H.
DIV=’0’
DIV=’1’
Output Driver Select
The transmit data output pin TxD can be configured as push/pull or open
drain output chracteristic.
ODS=’0’
ODS=’1’
Invert Carrier Detect Pin Polarity
ICD=’0’
ICD=’1’
Request To Send Pin Control
The request to send pin RTS can be controlled by SEROCCO-M as an
output autonomously or via setting/clearing bit ’RTS’.
This bit is not valid in clock mode 4.
RTS=’0’
RTS=’1’
No Data Inversion.
Data is transmitted/received inverted (on a per bit basis).
In HDLC and HDLC Synchronous PPP modes the
continuous ’1’ idle sequence is NOT inverted. Thus it is
recommended to select the flag sequence for interframe
time fill transmission (CCR2H:ITF = ’1’), which is inverted.
TxD pin is open drain output.
TxD pin is push/pull output.
Carrier Detect (CD) input pin is active high.
Carrier Detect (CD) input pin is active low.
Pin RTS (output) pin is controlled by SEROCCO-M
autonomously.
HDLC Mode:
RTS is activated during transmission. In bus configuration
mode the functionality depends on bit field ’SOC’ setting.
Note: For autonomous RTS pin control a transmit clock is
ASYNC/BISYNC Mode:
The functionality depends on setting of bit ’FRTS’
Pin RTS can be controlled by software. The output level of
this pin depends on bit ’FRTS’.
necessary.
5-157
Register Description (CCR1H)
PEB 20532
PEF 20532
(all modes)
(all modes)
(all modes)
(all modes)
2000-09-14