peb20532 Infineon Technologies Corporation, peb20532 Datasheet - Page 164

• Manufacturer Part Number: peb20532
• Description: 2 Channel Serial Optimized Communication Controller
• Manufacturer: Infineon Technologies Corporation

Data Sheet
NPRE(1:0)
ITF
OIN
Number of Preamble Repetitions
This bit field determines the number of preambles transmitted:
NPRE = ’00’ 1 preamble.
NPRE = ’01’ 2 preambles.
NPRE = ’10’ 4 preambles.
NPRE = ’11’ 8 preambles.
Interframe Time Fill
This bit selects the idle state of the transmit pin TxD:
ITF=’0’
ITF=’1’
Note: It is recommended to clear bit ’ITF’ in bus configuration modes, i.e.
One Insertion
In HDLC mode a one-insertion mechanism similar to the zero-insertion
can be activated:
OIN=’0’
OIN=’1’
continuous ’1’s are sent as idle sequence and data encoding is
NRZ.
Continuous logical ’1’ is sent during idle phase.
HDLC Mode:
Continuous flag sequences are sent (’01111110’ flag
pattern).
BISYNC Mode:
Continuous SYN characters are output.
The ’1’ insertion mechanism is disabled.
In transmit direction a logical ’1’ is inserted to the serial
data stream after 7 consecutive zeros.
In receive direction a ’1’ is deleted from the receive data
stream after receiving 7 consecutive zeros.
This enables clock information to be recovered from the
receive data stream by means of a DPLL, even in the case
of NRZ data encoding, because a transition at bit cell
boundary occurs at least every 7 bits.
5-164
Register Description (CCR2H)
(hdlc/bisync mode)
(hdlc/bisync mode)
PEB 20532
PEF 20532
(hdlc mode)
2000-09-14