peb20532 Infineon Technologies Corporation, peb20532 Datasheet - Page 44

• Manufacturer Part Number: peb20532
• Description: 2 Channel Serial Optimized Communication Controller
• Manufacturer: Infineon Technologies Corporation

PEB 20532
PEF 20532
Functional Overview
32 byte Shadow part
(not accessable by CPU)
32 byte Receive Pool
(accessable by CPU)
Figure 10
SCC Receive FIFO
New receive data is announced to the CPU with an interrupt latest when the FIFO fill
level reaches a chosen threshold level (selected with bitfield ’RFTH(1..0)’ in register
“CCR3H” on Page
167). Default value for this threshold level is 32 bytes in HDLC/PPP
modes and 1 byte in ASYNC or BISYNC mode.
If the SCC receive FIFO is completely filled, further incoming data is ignored and a
receive data overflow condition (’RDO’) is detected. As soon as the receive FIFO
provides empty space, receive data is accepted again after a frame end or frame abort
sequence. The automatically generated receive status byte (RSTA) will contain an ’RDO’
indication in this case and the next incoming frame will be received in a normal way.
Therefore no further CPU intervention is necessary to recover the SCC from an ’RDO’
condition.
A "frame" with ’RDO’ status might be a mixture of a frame partly received before the
’RDO’ event occured and the rest of this frame received after the receive FIFO again
accepted data and the frame was still incoming. A quite arbitrary series of data or
complete frames might get lost in case of an ’RDO’ event. Every frame which is
completely discarded because of an ’RDO’ condition generates an ’RFO’ interrupt.
The SCC receive FIFO can be cleared by command ’RRES’ in register CMDRH. Note
that clearing the receive FIFO during operation might delete a frame end / block end
indication. A frame which was already partly transferred cannot be "closed" in this case.
A new frame received after receiver reset command will be appended to this "open"
frame.
Data Sheet
44
2000-09-14