peb20532 Infineon Technologies Corporation, peb20532 Datasheet - Page 207
peb20532
Manufacturer Part Number
peb20532
Description
2 Channel Serial Optimized Communication Controller
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PEB20532.pdf
(282 pages)
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Data Sheet
Register 69
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
Register 70
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
Bit
Bit
H
A
B
H
A
B
7
0
0
7
0
0
AMRAL2
Mask Receive Address 2 Low Register
AMRAH2
Mask Receive Address 2 High Register
6
0
0
6
0
0
read/write
00
Channel A
46
written by CPU;
read and evaluated by SEROCCO-M
read/write
00
Channel A
47
written by CPU;
read and evaluated by SEROCCO-M
H
H
H
H
5
0
0
5
0
0
Receive Mask Address 2 (high)
Receive Mask Address 2 (low)
Channel B
96
Channel B
97
H
H
5-207
4
0
0
4
0
0
AMRAH2
AMRAL2
3
0
0
3
0
0
Register Description (AMRAL2)
2
2
0
0
0
0
1
1
0
0
0
0
PEB 20532
PEF 20532
2000-09-14
0
0
0
0
0
0
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