qf4a512 ETC-unknow, qf4a512 Datasheet - Page 18

• Manufacturer Part Number: qf4a512
• Description: 4-channel Programmable Signal Converter Psc
• Manufacturer: ETC-unknow

6.4 Input Voltage Levels
Ideally the maximum input voltage to the QF4A512 should correspond to a full-scale reading from the ADC. If the input signal level is
too low to achieve this, then PGA gain can be introduced to provide a larger signal to the ADC. If the input signal is too high then it
should be attenuated to prevent clipping (see section 13 for suggested input circuit configurations). Positive full-scale output from the
ADC (7FFFh) will occur when the positive input, A
(8000h) will occur when A
Internally, each input is biased to 1.2V, with a recommended input voltage range from 0.5V to 2.5V. This limits the negative swing on
the input to -0.7V so to achieve full scale output from the ADC the input swing would be limited to +/-0.5V (with respect to the 1.2V bias)
and a PGA gain of x2 would be selected.
This subject is covered in more detail in Application Note QFAN004, Interfacing Analog Signals to the QF4A512 programmable Signal
Converter.
6.5 Anti-Aliasing Filter (AAF)
The Anti-Aliasing Filter is designed to reject frequencies that are higher than the band of interest. If those frequencies are sent to the
ADC, they can alias back into the band of interest and can cause erroneous readings to result. The AAF is a 3rd order Bessel function
(linear phase) and is set to the appropriate cut-off frequency based on the filter design that is implemented. The AAF has two available
cut off frequencies, 500kHz and 3MHz.
The anti-aliasing filter has two frequency cutoff settings which are also configured by the Quickfilter Pro software. If desired the value
can be verified in register CHn_CFG (where n is the channel of interest). Either 0.5MHz or 3MHz can be selected according to the
frequency of interest for each particular channel.
6.6 Enabling Channels
For a given channel to be active and produce digital output data the following conditions must be met:
To disable a channel it is only necessary to set the corresponding disable bit in the GLBL_CH_CTRL register, this setting will override
the ENABLE register bit settings described above.
Rev C5, Jan 07
a) ADC and system clock enabled (Register ENABLE_0, control bits pcg_ch_enb).
b) AAF enabled (Register ENABLE_1, control bits afe_opmfec).
c) Sampling of the designated channel enabled and demuxing to the selected output data stream (Register ENABLE_2, control bits
d) Channel designated to be present in the output data stream (Register ENABLE_2, control bits sif_ch_enab)
e) Channel enabled in the global channel control register (Register GLBL_CH_CTRL, control bit chn_pwrd, where n is the channel
arec_ch_enab).
number)
IN+
A
A
is 1V more negative than A
IN+
IN-
+
-
Figure 5. QF4A412 Input schematic
1.2V DC
Internal
1.2V DC
Internal
10K
10K
IN+
1V2
1V2
, is 1V more positive than the negative input, A
IN-
PRELIMINARY
.
18
-
+
-
+
Internal
Internal
7.5K
7.5K
To Summing Stage
To Summing Stage
IN-
. Negative full scale output
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QF4A512