qf4a512 ETC-unknow, qf4a512 Datasheet - Page 35

• Manufacturer Part Number: qf4a512
• Description: 4-channel Programmable Signal Converter Psc
• Manufacturer: ETC-unknow

Table 17. Control Register listing (High-Level, EEPROM Startup, Run & Status)
12.2 High-level Registers
Note: * denotes default values
00h GLBL_SW (User Register)
Address 00h D7
Description: Global Software is provided as a blank user byte for the programmer to read and write to as a test. This byte defaults to 0
at power up and is not loaded from EEPROM.
01h GLBL_ID (Chip ID) - READ ONLY
Address 01h ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
[ID7:ID0] = Identification number of the QF4A512, default = A0h (was B1h on pre-production devices).
Description: This read-only byte contains a number describing the identification of the QF4A512 device. This data is hard-wired and is
not transferred from EEPROM. It can be read at any time.
Note: Revision information can be found in the DIE_REV register (EAh)
02h FULL_SRST (Global Soft Reset)
Address 02h
glbl_srst
* 0 = Does nothing.
Rev C5, Jan 07
000Ch PLL_SIF_STAT
000Dh
000Ah
000Bh
000Eh
000Fh ADC_STATUS_0
0000h
0001h
0002h
0003h GLBL_CH_CTRL
0004h
0005h
0006h
0007h
0008h
0009h
0010h ADC_STATUS_1
Hex*
Register Name
EE_STATUS
FULL_SRST
STARTUP_1
STARTUP_2
RUN_MODE
EE_TRANS
ENABLE_0
ENABLE_1
ENABLE_2
GLBL_SW
EE_COPY
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
GLBL_ID
EE_VAL
X
D6
X
D5
X
Software Register, Test Reads and Writes
Chip ID Including Revision Number.
Activates all soft resets
Reset, Enable or Power Down each channel
Set chip in Run or Configure Mode
Control data transfers to/from EEPROM
Control full transfers to/from EEPROM
Set startup configuration, rate for EEPROM clock
Initialization delay counter
Enable ADC and system clock per channel
Enable AAF per channel, ADC operation mode
Designate active channels
PLL lock, SIF address out of range
EEPROM status register value
EEPROM transfer status flags
ADC out of range, per channel
ADC out of range, high or low, per channel
D4
X
D3
X
D2
X
Description
D1
X
glbl_srst
D0
Bit 0
PRELIMINARY
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QF4A512