qf4a512 ETC-unknow, qf4a512 Datasheet - Page 39

• Manufacturer Part Number: qf4a512
• Description: 4-channel Programmable Signal Converter Psc
• Manufacturer: ETC-unknow

1 = Enabled
Description: Enables the ADC clock and system clock for channel N.
0Ah ENABLE_1 (AAF Enable, ADC Mode)
Address 0Ah
afe_opmfecN
* 0 = Powered Down
Description: Enables the anti-aliasing filter for channel N. Must be enabled for the channel to be used, this bit is for power savings on
disabled channels.
afe_opmadc
* 00 = Powered Down (10uW, 5us)
01 = Sleep (2mW, 0.5us)
10 = Standby (22mW, 12 clock cycles)
11 = Active (80mW)
Description: Sets the operating mode of the ADC. These bits can be used to conserve power in duty cycle applications. The mode can
be chosen to trade off power savings versus time to return to an active state (approximate values as shown).
0Bh ENABLE_2 (Sampling Enable, Serial output enable)
Address 0Bh sif_ch_en4 sif_ch_en3 sif_ch_en2 sif_ch_en1 arec_ch_en4 arec_ch_en3 arec_ch_en2 arec_ch_en1
arec_ch_enN
*1 = Enabled
Description: Controls the input mux and enables sampling for channel N. This bit should be disabled only for power savings on unused
channels. Disabling a channel will alter the effective sampling rate for the remaining active channels.
*0 = Disabled
1 = Enabled
Description: Controls the output mux. In multi-channel mode enables channel N in the serial output data stream. In single-channel
mode identifies which channel is enabled in the serial output data stream. If two or more bits are set the lowest channel set will be
output.
0Ch PLL_SIF_STAT (PLL status, serial interface status)
Address 0Ch
pll_lock – READ ONLY
* 0 = Not locked.
1 = Locked.
Description: Indicates PLL lock status.
ism_pll_lock – AUTO SET, may be reset by user
* 0 = Not locked.
Rev C5, Jan 07
1 = Enabled
0 = Disabled
Sif_ch_enN
Bit 7 Bit 6
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
X
X
Bit 7
X
X
afe_opmadc1 afe_opmadc0 afe_opmfec4 afe_opmfec3 afe_opmfec2 afe_opmfec1
X
Bit 6
Bit 5
X
X
Bit 5
X
Bit 4
ism_pll_lock pll_lock
Bit 1
Bit 4
Bit 3
Bit 0
PRELIMINARY
Bit 3
39
Bit 2
Bit 2
Bit 1
Bit 1
Bit 0
Bit 0
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QF4A512