qf4a512 ETC-unknow, qf4a512 Datasheet - Page 21

• Manufacturer Part Number: qf4a512
• Description: 4-channel Programmable Signal Converter Psc
• Manufacturer: ETC-unknow

7.8 Factory Calibration
Device level calibration can be performed during product test. However such calibration will not be as useful as system-level calibration
performed by the user. Therefore, by default, factory calibration is NOT performed. Please contact Quickfilter to discuss any
requirements you have for factory calibration.
7.9 User (System-level) Calibration
Overall system level performance can be improved if a system level calibration is performed. Using this technique gain and offset errors
introduced by variation in external components as well components internal to the QF4A512 itself can be minimized. To achieve this
improvement, provision must be made in the user’s application circuit to short the input to the channel of interest (for offset calibration)
and to apply a known fixed voltage (for gain calibration). The calculated gain and offset calibration values are written to the appropriate
CAL_n_GAIN and CAL_n_OFF registers.
Typically this sequence would be performed first for the offset calibration and then repeated (after adjusting cal_gain_mode and
CAL_DTGT accordingly) for gain calibration.
For gain calibration the target value (CAL_DTGT) will depend on the input voltage applied and the PGA gain setting for the channel.
For example, a full scale (positive) reading of the ADC would be 7FFFh for a 1V input (to the ADC). If the PGA gain is set to x2 this
would correspond to a +0.5V differential voltage at the device input pins. In practice a fixed input voltage in the range of 75-80% of full
scale and the corresponding ADC output value would typically be used – allowing for some headroom for offset calibration and to
prevent “clipping” of the ADC output for slightly over-range input voltages.
Note: The method described above is ideal if the QF4A512 configuration is static in the user’s application. If the application calls for
dynamically altering the configuration (for example PGA gain), or if a single design is used for multiple applications with differing
configurations, it may be beneficial to take multiple calibration readings, one for each configuration. In this case the multiple calibration
values could be stored in User EEPROM and transferred to the calibration registers at power up (or reset) by means of an extended
initialization sequence tailored for the desired configuration. This is the same technique that is used to transfer the factory calibration
data to the appropriate calibration registers. Indeed, if user calibration is performed it may be convenient to replace the default factory
calibration values with the user measured values.
Rev C5, Jan 07
To perform a user calibration the CAL_CTRL (EDh) and CAL_DTGT (EEh) registers are used:
1.
2.
3.
4.
5.
6.
7.
The cal_chan_set bits are written to select the channel, n, to be calibrated. (00 = channel 1, 01 = channel 2 …11= channel 4)
The cal_gain_mode bit selects whether offset (0) or gain (1) calibration is being performed.
The CAL_DTGT register holds the desired target value (ADC output value) for the voltage applied to the input. It should be set
to zero for offset calibration.
The cal_enab bit is then written to start the calibration measurement.
The resultant calibration value is written to the CAL_n_GAIN (if doing a gain calibration) or CAL_n_OFF (if doing offset
calibration) register.
Completion of the test is indicated by DRDY going high (and the cal_enab bit will auto clear).
To make this calibration data non-volatile the CAL_n_GAIN and CAL_n_OFF register values should be copied to EEPROM
((see Section 11.2)) after the calibration measurement is complete.
PRELIMINARY
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