qf4a512 ETC-unknow, qf4a512 Datasheet - Page 42

• Manufacturer Part Number: qf4a512
• Description: 4-channel Programmable Signal Converter Psc
• Manufacturer: ETC-unknow

10 = PLLCLK/8
11 = PLLCLK/16
Description: Clock for the analog front end and ADC blocks.
Afe_clk_inv
*0 = No inversion
1 = Inverted
Description: Inverts the clock input to the ADC. This setting should not be altered.
14h SYS_CLK_CTRL (System Clock Control)
Address 14h
sysclk_rate
*000 = PLL clock rate
Description: System clock. Frequency is PLLCLK/2
csifee_en
0 = Disabled
*1 = Inverted
Description: Enables clk_sifee, the clock for EEPROM transfers.
15h SPI_CTRL (Serial Interface Control)
Address 15h
ram_run_mode
*0 = Disabled
1 = Enabled
Description: Keeps RAM contents updated. Disable only during access to internal RAM from the SPI bus in configure mode. Usually will
be enabled with run mode once the coefficient RAMs have been configured.
sif_singlech
*0 = multi-channel mode
1 = Single channel mode
Description: Sets configuration of output data in run mode.
sif_par
*0 = No parity
1 = Parity enabled
Description: If set and in multi-channel mode, each channel’s MSB will toggle so the total number of “ones” is always odd.
sif_autoinc
*0 = Disable
1 = Enable
Description: Enable address autoincrement. If set, on the next read/write cycle the address data can be followed by multiple data bytes.
fast_ch
Rev C5, Jan 07
Bit 7 Bit 6 Bit 5
Bit 7
X
X
reserved fast_ch1 fast_ch0 sif_autoinc sif_par sif_singlech ram_run_mode
X
Bit 6
X
csifee_en
Bit 5
Bit 4
Bit 4
Bit 3
X
sysclk_rate2 sysclk_rate1 sysclk_rate0
Bit 2
Bit 3
N
, where N is the 3-bit value. Maximum value for N is 6 (divide by 64).
Bit 2
PRELIMINARY
Bit 1
42
Bit 1
Bit 0
Bit 0
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QF4A512