qf4a512 ETC-unknow, qf4a512 Datasheet - Page 23

• Manufacturer Part Number: qf4a512
• Description: 4-channel Programmable Signal Converter Psc
• Manufacturer: ETC-unknow

8.3 FIR Latency
There will be a delay introduced to the signal as it passes through the QF4A512. There are several components to this latency:
The dominant influence on the overall latency will be the fourth item. The delay introduced by the FIRs is given by:
FIR Delay = (# taps – 1)/2 * 1/f
The PGA + AAF latency = 0.7us (approx) if f
The ADC latency is equal to 9 ADC clock cycles = 9*N/(ADC clock rate)
The CIC/CIH latency = 28.5 / f
For an ADC clock rate of 75MHz, a single channel sampling at 10kHz would result in latencies of:
8.4 Maximum number of taps
There may be situations where it is not possible to implement a filter using all 512 taps. At high sampling rates it may not be possible to
implement all 512 taps within the maximum available sys_clk rate. The equation which determines this is as follows:
Example: sys_clk = 200MHz (max allowed value), fs = 2MHz → Maximum number of taps = 200.
Rev C5, Jan 07
Note: The latency for a specific configuration is calculated and displayed on the Config panel within the Quickfilter Pro software.
512 tap (maximum) filter:
100 tap filter:
1.
2.
3.
4.
5.
PGA and AAF
ADC
CIC and CIH filters (Filter 0)
FIR filters (Filter 1), up to 512 taps – delay determined by user–specified filter response.
Number of active channels (N).
Max Taps = 2 * Sys_clk/f
10000000
1000000
100000
10000
1000
100
10
s
s
Latency = 28.4ms (=0.7us + 9/75MHz + 28.5/10kHz + 255.5/10kHz)
Latency = 7.8ms (=0.7us + 9/75MHz + 28.5/10kHz + 49.5/10kHz)
0
s
Figure 6. Maximum Taps vs. Sample Rate vs. Sys Clk
200 MHz Sys Clk Rate
100 MHz
50 MHz
25 MHz
12.5 MHz
6.25 MHz
3.125 MHz
s
<800kHz, or 0.12us (approx) if f
100
PRELIMINARY
200
23
Maximum # Of Taps
300
s
>800kHz.
400
500
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600
QF4A512