qf4a512 ETC-unknow, qf4a512 Datasheet - Page 41

• Manufacturer Part Number: qf4a512
• Description: 4-channel Programmable Signal Converter Psc
• Manufacturer: ETC-unknow

Description: Indicates an underflow condition for the ADC on channel N.
12.5 Global Configuration Registers
Table 17. Control Register listing (Global Configuration)
11h PLL_CTRL_0 (PLL pre-divider and range)
Address 11h
pll_m
Description: A 6-bit number designating the value of the PLL pre-divider (M). Default value is 1.
pll_range
0 = 20 – 100 MHz
*1 = 100 – 200 MHz
Description: Set the range of the PLL clock which supplies the ADC and system clocks.
12h PLL_CTRL_1 (PLL loop divider)
Address 12h
Pll_n
Description: A 6-bit number designating the value of the PLL loop divider (N). Default value is 10.
13h ADC_CLK_RATE (ADC Clock Rate)
Address 13h
adcclk_rate
*00 = PLL clock/2
01 = PLLCLK/4
Rev C5, Jan 07
001Ch
001Ah CHIP_STADDR
001Bh
0011h
0012h
0013h ADC_CLK_RATE
0014h SYS_CLK_CTRL
0015h
0016h
0017h
0018h
0019h
Hex*
CHIP_STADDR
Register Name
PLL_CTRL_0
PLL_CTRL_1
EE_STADDR
EE_STADDR
END_ADDR
END_ADDR
SPI_CTRL
SPI_MON
Bit 7
Bit 7 Bit 6 Bit 5
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
X
X
X
pll_range pll_m5 pll_m4 pll_m3 pll_m2 pll_m1 pll_m0
X
X
Bit 6
pll_n5 pll_n4 pll_n3 pll_n2 pll_n1 pll_n0
X
Bit 5
PLL Pre-divider, frequency range.
PLL loop divider.
Clock rate for ADC, CRC and AREC.
System Clock control.
Set single-, multi-channel mode
Monitor internal data transfers
EE start address for block transfers (byte0)
EE start address for block transfers (byte1)
Chip start address for block transfers (byte0)
Chip start address for block transfers (byte1)
Ending address for block transfers (byte0)
Ending address for block transfers (byte1)
X
Bit 4
X
Bit 4
Bit 3
afe_clk_inv adcclk_rate1 adcclk_rate0
Bit 2
Description
Bit 3
Bit 2
Bit 2
Bit 1
Bit 1
Bit 0
Bit 1
PRELIMINARY
41
Bit 0
Bit 0
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QF4A512