qf4a512 ETC-unknow, qf4a512 Datasheet - Page 45

• Manufacturer Part Number: qf4a512
• Description: 4-channel Programmable Signal Converter Psc
• Manufacturer: ETC-unknow

Description: Soft reset of internal blocks. User resets can be performed in register FULL_SRST (02h).
27h ADC_CTRL (ADC control) - LOCKED
Address 27h
28h AREC_CTRL (ADC Pipeline latency) - LOCKED
Address 28h
Description: Programmable ADC pipeline latency. Default value is 9, allowable range is 6 – 10.
29h PMUX (Test Mux) – Factory use only (Default value = 0)
2Ah DEBUG (Debug mode) – Factory use only (Default value = 0)
2Bh PCG_MNTNC (PCG maintenance) – Factory use only (Default value = 0)
2Ch CAL_AFE (AFE Calibration) – Factory use only (Default value = 1)
2Dh BIST_CTRL (BIST control) – Factory use only (Default value = 0)
2Eh BIST_STATUS_0 (BIST status) – Factory use only (Default value = 0)
2Fh BIST_STATUS_1 (BIST status) – Factory use only (Default value = 0)
12.7 Channel-specific Registers
Table 19. Channel-specific Register Map
The following descriptions show the address for Channel 1. The maps for the other three channels are identical with address offsets of
30h for Channel 2, 60h for Channel 3 and 90h for Channel 4, as shown in the table above.
Run and Status Registers
30h CH1_PGA (Programmable Gain Amplifier Setting, FIR bypass)
Rev C5, Jan 07
Channel
0030h -
0031h
0032h –
0050h
0051h –
0059h
005Ah –
005Fh
1
0060h -
0061h
0062h –
0080h
0081h –
0089h
008Ah –
008Fh
Channel
Bit 7 Bit 6 Bit 5 Bit 4
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
X
X
2
X
X
Channel
0090h -
0091h
0092h –
00B0h
00B1h –
00B9h
00Bah –
00BFh
X
X
3
X
X
Channel
00C0h –
00C1h
00C2h –
00E0h
00E1h –
00E9h
00EAh –
00EFh
afe_dcr_en afe_adc_shin afe_sub_samp1 afe_sub_samp0
4
D3
Bit 3
D2
Run & Status
Configuration
Maintenance
Function
Reserved
D1
Bit 2
D0
PRELIMINARY
Bit 1
45
Bit 0
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QF4A512