sak-c868p-1rr Infineon Technologies Corporation, sak-c868p-1rr Datasheet - Page 128
![no-image](/images/no-image-200.jpg)
sak-c868p-1rr
Manufacturer Part Number
sak-c868p-1rr
Description
8 - Bit Cmos Microcontroller
Manufacturer
Infineon Technologies Corporation
Datasheet
1.SAK-C868P-1RR.pdf
(266 pages)
- Current page: 128 of 266
- Download datasheet (4Mb)
The register TRPCTR controls the trap functionality. It contains independent enable bits
for each output signal and control bits to select the behavior in case of a trap condition.
The trap condition is a low level on the CTRAP input pin, which is monitored (inverted
level) by bit TRPF (in register IS). While TRPF=’1’ (trap input active), the trap state bit
TRPS (in register IS) is set to ’1’.
TRPCTRL
Trap Control Register ,Low Byte
Field
TRPM1,
TRPM0
User’s Manual
7
-
r
6
-
r
Bits
[1:0]
5
-
r
Type Description
rw
Trap Mode Control Bits 1, 0
These two bits define the behavior of the selected
outputs when leaving the trap state after the trap
condition has become inactive again.
A synchronization to the timer driving the PWM
pattern permits to avoid unintended short pulses
when leaving the trap state. The combination
(TRPM1, TRPM0) leads to:
00
01
10
11
4
-
r
The trap state is left (return to normal
operation according to TRPM2) when a zero-
match of T12 (while counting up) is detected
(synchronization to T12).
The trap state is left (return to normal
operation according to TRPM2) when a zero-
match of T13 is detected (synchronization to
T13).
reserved
The trap state is left (return to normal
operation according to TRPM2) immediately
without any synchronization to T12 or T13.
4-84
3
-
r
On-Chip Peripheral Components
TRPM2
rw
2
TRPM1
[Reset value: 00
rw
1
V 1.0, 2003-01
TRPM0
rw
C868
0
H
]
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