sak-c868p-1rr Infineon Technologies Corporation, sak-c868p-1rr Datasheet - Page 183

• Manufacturer Part Number: sak-c868p-1rr
• Description: 8 - Bit Cmos Microcontroller
• Manufacturer: Infineon Technologies Corporation

6.1.2
When the reset input to the Watchdog Timer, the Watchdog Timer is automatically
enabled. Once disabled by setting SCUWDT.WDTDIS, it can only be enabled again by
a reset. Setting SCUWDT.WDTEOI will render SCUWDT.WDTDIS ineffective. If the
software fails to clear the watchdog timer an internal reset will be initiated. The reset
cause (external reset or reset caused by the watchdog) can be examined by software
(status flag SCUWDT.WDTR). A refresh of the watchdog timer is done by setting bits
SCUWDT.WDTRE and SCUWDT.WDTRS consecutively. This double instruction
sequence has been implemented to increase system security.
It must be noted, however, that the watchdog timer is halted during the idle mode and
power-down mode of the processor (see section "Power Saving Modes"). It is not
possible to use the idle mode in combination with the watchdog timer function.
Therefore, even the watchdog timer cannot reset the device when one of the power
saving modes has been entered accidentally.
6.1.3
At the same time the watchdog timer is started, the 8-bit register WDTH is preset by the
contents of WDTREL. Once enabled and the SCUWDT.WDTEOI is set the watchdog
cannot be stopped by software but can only be refreshed to the reload value by first
setting
SCUWDT.WDTR will automatically be cleared during the second machine cycle after
having been set. For this reason, setting SCUWDT.WDTRS bit has to be a one cycle
instruction (e.g. SETB WDTRS). This double-instruction refresh of the watchdog timer is
implemented to minimize the chance of an unintentional reset of the watchdog.
The reload register WDTREL can be written to at any time, as already mentioned.
Therefore, a periodical refresh of WDTREL can be added to the above mentioned
starting procedure of the watchdog timer. Thus a wrong reload value caused by a
possible distortion during the write operation to the WDTREL can be corrected by
software.
User’s Manual
bit
Starting the Watchdog Timer
Refreshing the Watchdog Timer
SCUWDT.WDTRE
and
6-5
SCUWDT.WDTRS
Fail Save Mechanism
consecutively.
V 1.0, 2003-01
C868
Bit