at90pwm81-16se ATMEL Corporation, at90pwm81-16se Datasheet - Page 144

• Manufacturer Part Number: at90pwm81-16se
• Description: 8-bit Avr Microcontroller With 8k Bytes In- System Programmable Flash
• Manufacturer: ATMEL Corporation

13.26.3
144
AT90PWM81
PSC2 Interrupt Flag Register – PIFR2
Bit
Read/Write
Initial Value
• Bit 7 – POACnB : PSC n Output B Activity
This bit is set by hardware each time the output PSCOUTn1 changes from 0 to 1 or from 1 to 0.
Must be cleared by software by writing a one to its location.
This feature is useful to detect that a PSC output doesn’t change due to a frozen external input signal.
• Bit 6 – POACnA : PSC n Output A Activity
This bit is set by hardware each time the output PSCOUTn0 changes from 0 to 1 or from 1 to 0.
Must be cleared by software by writing a one to its location.
This feature is useful to detect that a PSC output doesn’t change due to a frozen external input signal.
• Bit 5 – PSEIn : PSC n Synchro Error Interrupt
This bit is set by hardware when the update (or end of PSC cycle) of the PSCn configured in auto run
(PARUNn = 1) does not occur at the same time than the PSCn-1 which has generated the input run signal.
(For PSC0, PSCn-1 is PSC2).
Must be cleared by software by writing a one to its location.
This feature is useful to detect that a PSC doesn’t run at the same speed or with the same phase than the
PSC master.
• Bit 4 – PEVnB : PSC n External Event B Interrupt
This bit is set by hardware when an external event which can generates a capture or a retrigger from
Retrigger/Fault block B occurs.
Must be cleared by software by writing a one to its location.
This bit can be read even if the corresponding interrupt is not enabled (PEVEnB bit = 0).
• Bit 3 – PEVnA : PSC n External Event A Interrupt
This bit is set by hardware when an external event which can generates a capture or a retrigger from
Retrigger/Fault block A occurs.
Must be cleared by software by writing a one to its location.
This bit can be read even if the corresponding interrupt is not enabled (PEVEnA bit = 0).
• Bit 2:1 – PRNn1:0 : PSC n Ramp Number
Memorization of the ramp number when the last PEVnA or PEVnB occurred.
Table 13-22.
PRNn1
0
PRNn0
0
7
POAC2B
R
0
PSC n Ramp Number Description
6
POAC2A
R
0
Description
The last event which has generated an interrupt occurred during ramp 1
5
PSEI2
R/W
0
4
PEV2B
R/W
0
3
PEV2A
R/W
0
2
PRN21
R
0
1
PRN20
R
0
0
PEOP2
R/W
0
7734M–AVR–03/10
PIFR2