at90pwm81-16se ATMEL Corporation, at90pwm81-16se Datasheet - Page 20

• Manufacturer Part Number: at90pwm81-16se
• Description: 8-bit Avr Microcontroller With 8k Bytes In- System Programmable Flash
• Manufacturer: ATMEL Corporation

20
AT90PWM81
EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy
programming.
Table 5-1.
• Bit 3 – EERIE: EEPROM Ready Interrupt Enable
Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to
zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is
cleared. The interrupt will not be generated during EEPROM write or SPM.
• Bit 2 – EEMWE: EEPROM Master Write Enable
The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When
EEMWE is set, setting EEWE within four clock cycles will write data to the EEPROM at the selected
address If EEMWE is zero, setting EEWE will have no effect. When EEMWE has been written to one by
software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an
EEPROM write procedure.
• Bit 1 – EEWE: EEPROM Write Enable
The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are
correctly set up, the EEWE bit must be written to one to write the value into the EEPROM. The EEMWE
bit must be written to one before a logical one is written to EEWE, otherwise no EEPROM write takes
place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4
is not essential):
The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check
that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if
the software contains a Boot Loader allowing the CPU to program the Flash. If the Flash is never being
updated by the CPU, step 2 can be omitted. See
ming” on page 232
Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master
Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another
EEPROM access, the EEAR or EEDR Register will be modified, causing the interrupted EEPROM access
to fail. It is recommended to have the Global Interrupt Flag cleared during all the steps to avoid these
problems.
1.
2.
3.
4.
5.
6.
EEPM1
0
0
1
1
Wait until EEWE becomes zero.
Wait until SPMEN (Store Program Memory Enable) in SPMCSR (Store Program Memory Con-
trol and Status Register) becomes zero.
Write new EEPROM address to EEAR (optional).
Write new EEPROM data to EEDR (optional).
Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR.
Within four clock cycles after setting EEMWE, write a logical one to EEWE.
EEPM0
EEPROM Mode Bits
0
1
0
1
for details about Boot programming.
Programming
3.4 ms
1.8 ms
1.8 ms
Time
–
Operation
Erase and Write in one operation (Atomic Operation)
Erase Only
Write Only
Flush temporary EEPROM page buffer
“Boot Loader Support – Read-While-Write Self-Program-
7734M–AVR–03/10