c8051t617 Silicon Laboratories, c8051t617 Datasheet - Page 200

• Manufacturer Part Number: c8051t617
• Description: Mixed Signal Byte-programmable Eprom Mcu
• Manufacturer: Silicon Laboratories

C8051T610/1/2/3/4/5/6/7
SFR Definition 19.2. PCA0MD: PCA Mode
200
Bit7:
Bit6:
Bit5:
Bit4:
Bits3–1: CPS2–CPS0: PCA Counter/Timer Pulse Select.
Bit0:
Note:
CIDL
R/W
Bit7
CIDL: PCA Counter/Timer Idle Control.
Specifies PCA behavior when CPU is in Idle Mode.
0: PCA continues to function normally while the system controller is in Idle Mode.
1: PCA operation is suspended while the system controller is in Idle Mode.
WDTE: Watchdog Timer Enable
If this bit is set, PCA Module 4 is used as the watchdog timer.
0: Watchdog Timer disabled.
1: PCA Module 4 enabled as Watchdog Timer.
WDLCK: Watchdog Timer Lock
This bit locks/unlocks the Watchdog Timer Enable. When WDLCK is set, the Watchdog
Timer may not be disabled until the next system reset.
0: Watchdog Timer Enable unlocked.
1: Watchdog Timer Enable locked.
UNUSED. Read = 0b, Write = don't care.
These bits select the timebase source for the PCA counter
ECF: PCA Counter/Timer Overflow Interrupt Enable.
This bit sets the masking of the PCA Counter/Timer Overflow (CF) interrupt.
0: Disable the CF interrupt.
1: Enable a PCA Counter/Timer Overflow interrupt request when CF (PCA0CN.7) is set.
When the WDTE bit is set to ‘1’, the PCA0MD register cannot be modified. To change the contents
of the PCA0MD register, the Watchdog Timer must first be disabled.
*Note: External oscillator source divided by 8 is synchronized with the system clock.
CPS2
WDTE
0
0
0
0
1
1
1
1
R/W
Bit6
CPS1
WDLCK
0
0
1
1
0
0
1
1
R/W
Bit5
CPS0
0
1
0
1
0
1
0
1
R/W
Bit4
-
System clock divided by 12
System clock divided by 4
Timer 0 overflow
High-to-low transitions on ECI (max rate = system clock
divided by 4)
System clock
External clock divided by 8*
Reserved
Reserved
Rev. 0.3
CPS2
R/W
Bit3
CPS1
R/W
Bit2
Timebase
.
CPS0
R/W
Bit1
ECF
R/W
Bit0
SFR Address:
01000000
Reset Value
0xD9