c8051t617 Silicon Laboratories, c8051t617 Datasheet - Page 49

• Manufacturer Part Number: c8051t617
• Description: Mixed Signal Byte-programmable Eprom Mcu
• Manufacturer: Silicon Laboratories

5.6.2. Tracking Modes
The AD0TM bit in register ADC0CN enables "delayed conversions", and will delay the actual conversion
start by three SAR clock cycles, during which time the ADC will continue to track the input. If AD0TM is left
at logic 0, a conversion will begin immediately, without the extra tracking time. For internal start-of-conver-
sion sources, the ADC will track anytime it is not performing a conversion. When the CNVSTR signal is
used to initiate conversions, ADC0 will track either when AD0TM is logic 1, or when AD0TM is logic 0 and
CNVSTR is held low. See Figure 5.4 for track and convert timing details. Delayed conversion mode is use-
ful when AMUX settings are frequently changed, due to the settling time requirements described in Section
“5.6.3. Settling Time Requirements” on page 50.
Timer 0, Timer 2, Timer 1 Overflow
(AD0CM[2:0] = 000, 001, 010, 011)
Write '1' to AD0BUSY,
(AD0CM[2:0] = 1xx)
Figure 5.4. ADC Tracking and Conversion Timing
AD0TM = 1
AD0TM = 0
SAR Clocks
AD0TM = 1
AD0TM = 0
CNVSTR
Clocks
Clocks
Clocks
SAR
SAR
SAR
N/C
Track or
Convert
A. ADC Timing for External Trigger Source
B. ADC Timing for Internal Trigger Source
Track
Track
Track
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15* 16 17
1 2 3 4 5 6 7 8 9 10 11 12* 13 14
Rev. 0.3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15* 16 17
1 2 3 4 5 6 7 8 9 10 11 12* 13 14
C8051T610/1/2/3/4/5/6/7
Convert
*Conversion Ends at rising edge of 15
*Conversion Ends at rising edge of 12
*Conversion Ends at rising edge of 15
*Conversion Ends at rising edge of 12
Convert
Convert
Convert
th
th
th
clock in 8-bit Compatibility Mode
th
clock in 8-bit Compatibility Mode
clock in 8-bit Compatibility Mode
clock in 8-bit Compatibility Mode
Track
N/C
Track
Track
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