c8051t617 Silicon Laboratories, c8051t617 Datasheet - Page 98

• Manufacturer Part Number: c8051t617
• Description: Mixed Signal Byte-programmable Eprom Mcu
• Manufacturer: Silicon Laboratories

C8051T610/1/2/3/4/5/6/7
9.4.2. Stop Mode
Setting the Stop Mode Select bit (PCON.1) causes the CIP-51 to enter Stop mode as soon as the instruc-
tion that sets the bit completes execution. In Stop mode the internal oscillator, CPU, and all digital peripher-
als are stopped; the state of the external oscillator circuit is not affected. Each analog peripheral (including
the external oscillator circuit) may be shut down individually prior to entering Stop Mode. Stop mode can
only be terminated by an internal or external reset. On reset, the CIP-51 performs the normal reset
sequence and begins program execution at address 0x0000.
If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode.
The Missing Clock Detector should be disabled if the CPU is to be put to in STOP mode for longer than the
MCD timeout of 100 µsec.
By default, when in Stop Mode the internal regulator is still active. However, the regulator can be config-
ured to shut down while in Stop Mode to save power. To shut down the regulator in Stop Mode, the
STOPCF bit in register REG0CN should be set to “1” prior to setting the STOP bit (see SFR Definition 8.1).
If the regulator is shut down using the STOPCF bit, only the RST pin or a full power cycle are capable of
resetting the device.
Note: It is important to follow the instruction to enter Stop mode with one that does not access any SFRs or
RAM (such as a NOP). This will prevent additional supply current in Stop mode.
SFR Definition 9.12.
98
Bits7–2: GF5–GF0: General Purpose Flags 5–0.
Bit1:
Bit0:
GF5
R/W
Bit7
These are general purpose flags for use under software control.
STOP: Stop Mode Select.
Setting this bit will place the CIP-51 in Stop mode. This bit will always be read as 0.
1: CPU goes into Stop mode (internal oscillator stopped).
IDLE: Idle Mode Select.
Setting this bit will place the CIP-51 in Idle mode. This bit will always be read as 0.
1: CPU goes into Idle mode. (Shuts off clock to CPU, but clock to Timers, Interrupts, Serial
Ports, and Analog Peripherals are still active.)
GF4
R/W
Bit6
PCON: Power Control
GF3
R/W
Bit5
GF2
R/W
Bit4
Rev. 0.3
GF1
R/W
Bit3
GF0
R/W
Bit2
STOP
R/W
Bit1
IDLE
R/W
Bit0
SFR Address:
00000000
Reset Value
0x87