c8051t617 Silicon Laboratories, c8051t617 Datasheet - Page 52

• Manufacturer Part Number: c8051t617
• Description: Mixed Signal Byte-programmable Eprom Mcu
• Manufacturer: Silicon Laboratories

C8051T610/1/2/3/4/5/6/7
SFR Definition 5.4. ADC0CF: ADC0 Configuration
SFR Definition 5.5. ADC0H: ADC0 Data Word High Byte
52
Bits7–3: AD0SC4–0: ADC0 SAR Conversion Clock Period Bits.
Note:
Bit2:
Bit1:
Bit0:
Bits7–0: ADC0 Data Word High-Order Bits.
AD0SC4
R/W
R/W
Bit7
Bit7
SAR Conversion clock (CLK
equation, where AD0SC refers to the 5-bit value held in bits AD0SC4–0. SAR conversion
clock requirements are given in Table 5.1.
AD0LJST: ADC0 Left Justify Select.
0: Data in ADC0H:ADC0L registers are right-justified.
1: Data in ADC0H:ADC0L registers are left-justified.
AD08BE: 8-Bit Mode Enable.
0: ADC operates in 10-bit mode (normal).
1: ADC operates in 8-bit mode.
AMP0GN0: ADC Gain Control Bit.
0: Gain = 0.5
1: Gain = 1
ADC0H holds the upper 8 bits of output data from the most recently completed ADC0 con-
version. In 8-bit compatibility mode, the ADC0H register holds all 8 bits of the conversion
data word.
For AD0LJST = 0: Bits 7–2 are zero. Bits 1–0 are the upper 2 bits of the 10-bit ADC0 Data
Word.
For AD0LJST = 1: Bits 7–0 are the most-significant 8 bits of the 10-bit ADC0 Data Word.
If the Memory Power Controller is enabled (MPCE = '1'), AD0SC must be set to at least "00001" for
proper ADC operation.
AD0SC
AD0SC3
R/W
R/W
Bit6
Bit6
=
SYSCLK
--------------------- - 1
CLK
AD0SC2
R/W
R/W
Bit5
Bit5
SAR
–
AD0SC1
R/W
R/W
Bit4
Bit4
SAR
) is derived from system clock (SYSCLK) by the following
AD0SC0 AD0LJST AD08BE AMP0GN0 11111001
Rev. 0.3
R/W
R/W
Bit3
Bit3
R/W
R/W
Bit2
Bit2
R/W
R/W
Bit1
Bit1
R/W
R/W
Bit0
Bit0
SFR Address:
SFR Address:
00000000
Reset Value
Reset Value
0xBC
0xBE