mc9s08rd60fj Freescale Semiconductor, Inc, mc9s08rd60fj Datasheet - Page 119

• Manufacturer Part Number: mc9s08rd60fj
• Description: Hcs08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

8.6.4 Port D Registers (PTDD, PTDPE, and PTDDD)
Port D pins used as general-purpose I/O pins are controlled by the port D data (PTDD), data direction
(PTDDD), and pullup enable (PTDPE) registers.
PTDDn — Port D Data Register Bit n (n = 0–7)
PTDPEn — Pullup Enable for Port D Bit n (n = 0–7)
PTDDDn — Data Direction for Port D Bit n (n = 0–7)
Freescale Semiconductor
For port D pins that are inputs, reads return the logic level on the pin. For port D pins that are
configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port D pins that are configured as outputs, the logic
level is driven out the corresponding MCU pin.
Reset forces PTDD to all 0s, but these 0s are not driven out the corresponding pins because reset also
configures all port pins as high-impedance inputs with pullups disabled.
For port D pins that are inputs, these read/write control bits determine whether internal pullup devices
are enabled. For port D pins that are configured as outputs, these bits are ignored and the internal pullup
devices are disabled.
These read/write bits control the direction of port D pins and what is read for PTDD reads.
PTDD
PTDPE
PTDDD
1 = Internal pullup device enabled.
0 = Internal pullup device disabled.
1 = Output driver enabled for port D bit n and PTDD reads return the contents of PTDDn.
0 = Input (output driver disabled) and reads return the pin value.
Reset:
Reset:
Reset:
Read:
Read:
Read:
Write:
Write:
Write:
Bit 7
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 8-9 Port D Registers
PTDPE6
PTDDD6 PTDDD5 PTDDD4 PTDDD3 PTDDD2 PTDDD1 PTDDD0
PTDD6
6
0
0
0
MC9S08RC/RD/RE/RG
PTDPE5
PTDD5
5
0
0
0
PTDPE4
PTDD4
4
0
0
0
PTDPE3
PTDD3
SoC Guide — MC9S08RG60/D Rev 1.10
3
0
0
0
PTDPE2
PTDD2
2
0
0
0
PTDPE1
PTDD1
1
0
0
0
PTDPE0
PTDD0
Bit 0
0
0
0
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