mc9s08rd60fj Freescale Semiconductor, Inc, mc9s08rd60fj Datasheet - Page 68

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mc9s08rd60fj

Manufacturer Part Number
mc9s08rd60fj
Description
Hcs08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Resets, Interrupts, and System Configuration
COPE — COP Watchdog Enable
COPT — COP Watchdog Timeout
STOPE — Stop Mode Enable
BKGDPE — Background Debug Mode Pin Enable
RSTPE — RESET Pin Enable
68
This write-once bit defaults to 1 after reset.
This write-once bit defaults to 1 after reset.
This write-once bit defaults to 0 after reset, which disables stop mode. If stop mode is disabled and a
user program attempts to execute a STOP instruction, an illegal opcode reset is forced.
The BKGDPE bit enables the PTD0/BKGD/MS pin to function as BKGD/MS. When the bit is clear,
the pin will function as PTD0, which is an output only general purpose I/O. This pin always defaults
to BKGD/MS function after any reset.
The RSTPE bit enables the PTD1/RESET pin to function as RESET. When the bit is clear, the pin will
function as PTD1, which is an output only general purpose I/O. This pin always defaults to RESET
function after any reset.
1 = COP watchdog timer enabled (force reset on timeout).
0 = COP watchdog timer disabled.
1 = Long timeout period selected (2
0 = Short timeout period selected (2
1 = Stop mode enabled.
0 = Stop mode disabled.
1 = BKGD pin enabled.
0 = BKGD pin disabled.
1 = RESET pin enabled
0 = RESET pin disabled
Reset:
Read:
Write:
Figure 5-5 System Options Register (SOPT)
COPE
Bit 7
1
= Unimplemented or Reserved
COPT
6
1
MC9S08RC/RD/RE/RG
20
18
cycles of BUSCLK).
cycles of BUSCLK).
STOPE
5
0
4
1
3
0
0
2
0
0
BKGDPE
Freescale Semiconductor
1
1
RSTPE
Bit 0
1

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