mc9s08rd60fj Freescale Semiconductor, Inc, mc9s08rd60fj Datasheet - Page 200

• Manufacturer Part Number: mc9s08rd60fj
• Description: Hcs08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Development Support
BDFR — Background Debug Force Reset
14.5.3 DBG Registers and Control Bits
The debug module includes nine bytes of register space for three 16-bit registers and three 8-bit control
and status registers. These registers are located in the high register space of the normal memory map so
they are accessible to normal application programs. These registers are rarely if ever accessed by normal
user application programs with the possible exception of a ROM patching mechanism that uses the
breakpoint logic.
14.5.3.1 Debug Comparator A High Register (DBGCAH)
This register contains compare value bits for the high-order eight bits of comparator A. This register is
forced to $00 at reset and can be read at any time or written at any time unless ARM = 1.
14.5.3.2 Debug Comparator A Low Register (DBGCAL)
This register contains compare value bits for the low-order eight bits of comparator A. This register is
forced to $00 at reset and can be read at any time or written at any time unless ARM = 1.
14.5.3.3 Debug Comparator B High Register (DBGCBH)
This register contains compare value bits for the high-order eight bits of comparator B. This register is
forced to $00 at reset and can be read at any time or written at any time unless ARM = 1.
14.5.3.4 Debug Comparator B Low Register (DBGCBL)
This register contains compare value bits for the low-order eight bits of comparator B. This register is
forced to $00 at reset and can be read at any time or written at any time unless ARM = 1.
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A serial active background mode command such as WRITE_BYTE allows an external debug host to
force a target system reset. Writing logic 1 to this bit forces an MCU reset. This bit cannot be written
from a user program.
NOTES:
1. BDFR is writable only through serial active background mode debug commands, not from user programs.
Figure 14-6 System Background Debug Force Reset Register (SBDFR)
Reset:
Read:
Write:
Bit 7
0
0
= Unimplemented or Reserved
6
0
0
MC9S08RC/RD/RE/RG
5
0
0
4
0
1
3
0
0
2
0
0
Freescale Semiconductor
1
0
0
BDFR
Bit 0
0
0
(1)