mc9s08rd60fj Freescale Semiconductor, Inc, mc9s08rd60fj Datasheet - Page 172

• Manufacturer Part Number: mc9s08rd60fj
• Description: Hcs08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Serial Peripheral Interface (SPI) Module
12.4.2 SPI Control Register 2 (SPI1C2)
This read/write register is used to control optional features of the SPI system. Bits 7, 6, 5, and 2 are not
implemented and always read 0.
MODFEN — Master Mode-Fault Function Enable
BIDIROE — Bidirectional Mode Output Enable
SPISWAI — SPI Stop in Wait Mode
SPC0 — SPI Pin Control 0
172
When the SPI is configured for slave mode, this bit has no meaning or effect. (The SS1 pin is the slave
select input.) In master mode, this bit determines how the SS1 pin is used (refer to
details).
When bidirectional mode is enabled by SPI pin control 0 (SPC0) = 1, BIDIROE determines whether
the SPI data output driver is enabled to the single bidirectional SPI I/O pin. Depending on whether the
SPI is configured as a master or a slave, it uses either the MOSI1 (MOMI) or MISO1 (SISO) pin,
respectively, as the single SPI data I/O pin. When SPC0 = 0, BIDIROE has no meaning or effect.
The SPC0 bit chooses single-wire bidirectional mode. If MSTR = 0 (slave mode), the SPI uses the
MISO1 (SISO) pin for bidirectional SPI data transfers. If MSTR = 1 (master mode), the SPI uses the
MOSI1 (MOMI) pin for bidirectional SPI data transfers. When SPC0 = 1, BIDIROE is used to enable
or disable the output driver for the single bidirectional SPI I/O pin.
1 = Mode fault function enabled, master SS1 pin acts as the mode fault input or the slave select
0 = Mode fault function disabled, master SS1 pin reverts to general-purpose I/O not controlled by
1 = SPI I/O pin enabled as an output.
0 = Output driver disabled so SPI data I/O pin acts as an input.
1 = SPI clocks stop when the MCU enters wait mode.
0 = SPI clocks continue to operate in wait mode.
1 = SPI configured for single-wire bidirectional operation.
0 = SPI uses separate pins for data input and data output.
output.
SPI.
Reset:
Read:
Write:
Figure 12-8 SPI Control Register 2 (SPI1C2)
Bit 7
0
0
= Unimplemented or Reserved
6
0
0
MC9S08RC/RD/RE/RG
5
0
0
MODFEN BIDIROE
4
0
3
0
2
0
0
SPISWAI
Freescale Semiconductor
Table 12-1
1
0
SPC0
Bit 0
0
for more