mc9s12xf512 Freescale Semiconductor, Inc, mc9s12xf512 Datasheet - Page 823

• Manufacturer Part Number: mc9s12xf512
• Description: S12x Microcontrollers 16-bit Automotive Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

1. Incl. S12X_EBI registers
2. Refer to S12X_MMC section.
3. If EWAIT enabled for at least one CSx line (refer to S12X_MMC section), the minimum number of external bus cycles is 3.
4. Available only if configured appropriately by ROMON and EROMON (refer to S12X_MMC section).
18.4.2
Internal visibility allows the observation of the internal CPU address and data bus as well as the
determination of the access source and the CPU pipe (queue) status through the external bus interface.
Internal visibility is always enabled in emulation single chip mode and emulation expanded mode. Internal
CPU accesses are made visible on the external bus interface except CPU execution of BDM firmware
instructions.
Internal reads are made visible on ADDRx/IVDx (address and read data multiplexed, see
Table
show the type of access. External read data are also visible on IVDx.
During ‘no access’ cycles RW is held in read position while LSTRB is undetermined.
All accesses which make use of the external bus interface are considered external accesses.
Freescale Semiconductor
Data direction signals
threshold enabled on
Data select signals
(if 16-bit data bus)
address access
Reduced input
External wait
Chip Selects
(if Enabled)
Bus signals
Properties
Flash area
18-13), internal writes on ADDRx and DATAx (see
feature
Internal Visibility
(4)
Single-Chip
Normal
Single-Chip Modes
—
—
—
—
—
—
—
MC9S12XF - Family Reference Manual, Rev.1.19
Table 18-8. Summary of Functions
Single-Chip
Special
—
—
—
—
—
—
—
Signal Properties
ADDR[22:1]
DATA[15:0]
Expanded
Table 18-3
Normal
Refer to
EWAIT
UDS
LDS
CS0
CS1
CS2
CS3
WE
RE
—
Table 18-14
ADDR[22:20]/
ADDR[19:16]/
Single-Chip
ADDR[15:0]/
IQSTAT[3:0]
DATA[15:0]
DATA[15:0]
Emulation
IVD[15:0]
ACC[2:0]
ADDR0
LSTRB
1 cycle
EWAIT
Chapter 18 External Bus Interface (S12XEBIV4)
RW
—
—
Expanded Modes
to
Table
ADDR[22:20]/
ADDR[19:16]/
ADDR[15:0]/
IQSTAT[3:0]
Emulation
Expanded
DATA[15:0]
DATA[15:0]
IVD[15:0]
ACC[2:0]
18-16). RW and LSTRB
ADDR0
LSTRB
1 cycle
EWAIT
EWAIT
CS0
CS1
CS2
CS3
RW
Table 18-11
ADDR[22:0]
DATA[15:0]
Table 18-3
Special
Refer to
ADDR0
1 cycle
LSTRB
Test
RW
—
—
823
to