xr17v254 Exar Corporation, xr17v254 Datasheet - Page 17

• Manufacturer Part Number: xr17v254
• Description: 66mhz Pci Bus Quad Uart With Power Management Support
• Manufacturer: Exar Corporation

REV. 1.0.0
INT3, INT2 and INT1 [32:8]
Twenty four bit encoded interrupt indicator. Each channel’s interrupt is encoded into 3 bits for receive, transmit,
and status. bits [10:8] represent channel 0 and go up to channel 3 with bits [19:17]. Bits [31:20] are reserved.
The 3-bit encoding and their priority order are shown below in
the device and therefore they exist within channel 0 space and not in other channel interrupt.
.
F
RXRDY and RXRDY Time-out is clear by reading data in the RX FIFO until it falls below the trigger level.
RX Line Status interrupt clears after reading the LSR register that is in the UART channel register set.
TXRDY interrupt clears after reading ISR register that is in the UART channel register set.
Modem Status Register interrupt clears after reading MSR register that is in the UART channel register set.
RTS/CTS or DTR/DSR delta interrupt clears after reading MSR register that is in the UART channel register set.
Xoff/Xon delta and special char detect interrupt clears after reading the ISR register that is in the UART channel reg set.
TIMER Time-out interrupt clears after reading the TIMERCNTL register that is in the Device Configuration register set.
MPIO interrupt clears after reading the MPIOLVL register that is in the Device Configuration register set.
P
IGURE
RIORITY
N+2
Bit
1
2
3
4
5
6
7
x
Rsvd
N+1
Bit
5. T
B
IT
Bit
N
HE
[
0
0
0
0
1
1
1
1
N
INT3 Register
+2] B
G
N+2
Bit
LOBAL
Rsvd
N+1
Bit
IT
[
0
0
1
1
0
0
1
1
N
I
T
Bit
NTERRUPT
+1]
N
ABLE
N+2
T
Bit
ABLE
B
8: UART C
IT
Rsvd
N+1
0
1
0
1
0
1
0
1
Bit
66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT
[
N
R
]
9: UART C
EGISTER
Bit
N
None or wake-up indicator
RXRDY and RX Line Status (logic OR of LSR[4:1])
RXRDY Time-out
TXRDY, THR or TSR (auto RS485 mode) empty
MSR, RTS/CTS or DTR/DSR delta or Xoff/Xon det. or special char. detected
Reserved.
MPIO pin(s). Available only within channel 0, reserved in other channels.
TIMER Time-out. Available only within channel 0, reserved in other channels.
N+2
Bit
HANNEL
Rsvd
, INT0, INT1, INT2
INT0, INT1, INT2 and INT3
N+1
Bit
HANNEL
Interrupt Registers,
INT2 Register
Bit
N
[3:0] I
N+2
17
Bit
[3:0] I
Channel-3
NTERRUPT
N+1
Bit
NTERRUPT
Bit
Table 8
N
AND
I
NTERRUPT
N+2
Bit
S
INT3
Channel-2
OURCE
Rsvd
. The Timer and MPIO interrupts are for
N+1
Bit-7
Bit
C
LEARING
Rsvd Rsvd
Bit-6
S
Bit
N
E
OURCE
NCODING
Bit-5
N+2
Bit
Channel-1
(
INT0 Register
S
Rsvd
Bit-4
N+1
INT1 Register
Bit
)
Ch-3 Ch-2 Ch-1 Ch-0
Bit-3
Bit
N
N+2
Bit-2
Bit
Channel-0
XR17V254
N+1
Bit-1
Bit
Bit-0
Bit
N