xr17v254 Exar Corporation, xr17v254 Datasheet - Page 27

• Manufacturer Part Number: xr17v254
• Description: 66mhz Pci Bus Quad Uart With Power Management Support
• Manufacturer: Exar Corporation

REV. 1.0.0
The RX FIFO data (up to the maximum 64 bytes) can be read out in a single burst 32-bit read operation
(maximum 16 DWORD reads) at memory locations 0x100 (channel 0), 0x300 (channel 1), 0x500
(channel 2) and 0x700 (channel 3). This operation is at least 16 times faster than reading the data in 64
separate 8-bit memory reads of RHR register (0x000 for channel 0, 0x200 for channel 1, 0x400 for channel 2
and 0x600 for channel 3).
The XR17V254 also provides the same RX FIFO data along with the LSR status information of each byte side-
by-side, at locations 0x180 (channel 0), 0x380 (channel 1), 0x580 (channel 2) and 0x780 (channel 3). The
entire RX data along with the status can be downloaded in a single PCI Burst Read operation of 32 DWORD
reads. The Status and Data bytes must be read in 16 or 32 bits format to maintain data integrity. The following
tables show this clearly.
3.1.1
3.1.2
WITH N
WITH LSR
Read n+0 to n+3
Read n+4 to n+7
Data Bit-31
Read n+0 to n+1
Read n+2 to n+3
R
R
Data Bit-31
PCI Bus
PCI Bus
EAD
EAD
B7 B6 B5 B4 B3 B2 B1 B0
B7 B6 B5 B4 B3 B2 B1 B0
Etc.
RX FIFO,
RX FIFO,
Etc
Receive Data Byte n+3
O
Receive Data Byte n+1
Normal Rx FIFO Data Unloading at locations 0x100, 0x300, 0x500, 0x700
Special Rx FIFO Data Unloading at locations 0x180, 0x380, 0x580, and 0x780
E
E
RRORS
RRORS
Channel 0 to 3 ReceiveData in 32-bit alignment through the Configuration Register Address
Channel 0 to 1 Receive Data with Line Status Register in a 32-bit alignment through
FIFO Data n+3
FIFO Data n+7
FIFO Data n+1
FIFO Data n+3
B
B
YTE
B7 B6 B5 B4 B3 B2 B1 B0
YTE
B7 B6 B5 B4 B3 B2 B1 B0
66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT
Line Status Register n+1
Receive Data Byte n+2
3
3
the Configuration Register Address 0x0180 and 0x0380
0x0100, 0x0300, 0x0500 and 0x0700
FIFO Data n+2
FIFO Data n+6
LSR n+1
LSR n+3
B
B
YTE
YTE
27
B7 B6 B5 B4 B3 B2 B1 B0
B7 B6 B5 B4 B3 B2 B1 B0
2
2
Receive Data Byte n+1
Receive Data Byte n+0
FIFO Data n+1
FIFO Data n+5
FIFO Data n+0
FIFO Data n+2
B
B
YTE
YTE
1
1
B7 B6 B5 B4 B3 B2 B1 B0
B7 B6 B5 B4 B3 B2 B1 B0
Line Status Register n+0
Receive Data Byte n+0
FIFO Data n+0
FIFO Data n+4
XR17V254
LSR n+0
LSR n+2
B
B
YTE
YTE
Data Bit-0
Data Bit-0
PCI Bus
PCI Bus
0
0