xr17v254 Exar Corporation, xr17v254 Datasheet - Page 40

• Manufacturer Part Number: xr17v254
• Description: 66mhz Pci Bus Quad Uart With Power Management Support
• Manufacturer: Exar Corporation

XR17V254
66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT
SEE”RECEIVER” ON PAGE 39.
SEE”TRANSMITTER” ON PAGE 37.
The Baud Rate Generator (BRG) generates the data rate for the transmitter and receiver. The rate is
programmed through registers DLM, DLL and DLD which are only accessible when LCR bit [7] is set to logic 1.
Refer to
details.
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR) and also
encoded in INT (INT0-INT3) register in the Device Configuration Registers.
When the receive FIFO (FCR bit [0] = a logic 1) and receive interrupts (IER bit [0] = logic 1) are enabled, the
RHR interrupts (see ISR bits [4:3]) status will reflect the following:
A. The receive data available interrupts are issued to the host when the FIFO has reached the programmed
B. FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register
C. The receive data ready bit (LSR bit [0]) is set as soon as a character is transferred from the shift register to
F
5.0 UART CONFIGURATION REGISTERS
5.1
5.2
5.3
5.4
4.7.2
5.4.1
IGURE
trigger level. It will be cleared when the FIFO drops below the programmed trigger level.
status bit and the interrupt will be cleared when the FIFO drops below the trigger level.
the receive FIFO. It is reset when the FIFO is empty.
Receive Data
Byte and Errors
16X or 8X Sampling
Clock (8XMODE Reg.)
18. R
Receive Holding Register (RHR) - Read only
Transmit Holding Register (THR) - Write only
Baud Rate Generator Divisors (DLM, DLL and DLD)
Interrupt Enable Register (IER) - Read/Write
“Section 4.1, Programmable Baud Rate Generator with Fractional Divisor” on page 29
64 bytes by 11-
bit wide FIFO
Receiver Operation with FIFO
IER versus Receive FIFO Interrupt Mode Operation
ECEIVER
O
PERATION IN
Receive Data Shift
Register (RSR)
Receive Data
Receive
(64-byte)
FIFO
FIFO
Data
AND
F
Data falls to 40
FIFO Trigger=48
Data fills to 56
Validation
LOW
Data Bit
Example:
- FIFO trigger level set at 48 bytes
- RTS/DTR hyasteresis set at +/-8 chars.
C
40
ONTROL
RTS#/DTR# re-asserts when data falls below
the trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
RTS#/DTR# de-asserts when data fills above
the trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
RHR Interrupt (ISR bit-2) is programmed
at FIFO trigger level (RXTRG).
FIFO is Enable by FCR bit-0=1
M
ODE
Receive Data Characters
RXFIFO1
REV. 1.0.0
for more