xr17v254 Exar Corporation, xr17v254 Datasheet - Page 44
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xr17v254
Manufacturer Part Number
xr17v254
Description
66mhz Pci Bus Quad Uart With Power Management Support
Manufacturer
Exar Corporation
Datasheet
1.XR17V254.pdf
(70 pages)
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XR17V254
66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT
FCR[3]: DMA Mode Select
This bit has no effect since TXRDY and RXRDY pins are not available in this device. It is provided for legacy
software compatibility.
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•
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit [0] is active.
•
•
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit [0] is active.
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•
FCR[0]: TX and RX FIFO Enable
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•
Logic 0 = Set DMA to mode 0 (default).
Logic 1 = Set DMA to mode 1.
Logic 0= No transmit FIFO reset (default).
Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
Logic 0 = No receive FIFO reset (default).
Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
Logic 0 = Disable the transmit and receive FIFO (default).
Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are
written or they will not be programmed.
44
REV. 1.0.0