xr17v258 Exar Corporation, xr17v258 Datasheet - Page 14

• Manufacturer Part Number: xr17v258
• Description: 66mhz Pci Bus Octal Uart With Power Management Support
• Manufacturer: Exar Corporation

XR17V258
66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT
The V258 provides an interface to an Electrically Erasable Programmable Read Only Memory (EEPROM). The
EEPROM must be a 93C46-like device, with its memory configured as 16-bit words. This interface is provided
in order to program the registers in the PCI Configuration Space of the PCI UART during power-up. The
following table gives the mapping of the EEPROM memory to the registers in the V258’s PCI Configuration
Space. When the PCI RST# is negated, the V258 will download the data from the EEPROM, if it detects a
HIGH on the EECS pin. The V258 takes a maximum of 2
signal to read the EEPROM data. For more details on the EEPROM interface, please refer to the application
note DAN112 on Exar’s website.
N
The Device Configuration Registers and the eight individual UART Configuration Registers of the V258
occupy 4K of PCI bus memory address space. These addresses are offset onto the basic memory address, a
value loaded into the Memory Base Address Register (BAR) in the PCI local bus configuration register set. The
UART Configuration Registers are mapped into 8 address blocks where each UART channel occupies 512
bytes memory space for its own registers that include the 16550 compatible registers. The Device
Configuration Registers are embedded inside the UART channel zero’s address space between 0x0080 to
0x0093. All these registers can be accessed in 8, 16, 24 or 32 bits width depending on the starting address
given by the host at the beginning of the bus cycle. Transmit and receive data may be loaded or unloaded in 8,
16, 24 or 32 bits format in special locations given in the
made to the transmit or receive register, its FIFO data pointer is automatically bumped to the next sequential
data location either in byte, word or DWORD. One special case applies to the receive data unloading when
reading the receive data together with its LSR register content. The host must read them in 16 or 32 bits format
in order to maintain integrity of the data byte with its associated error flags. These special registers are further
discussed in
1.4
1.5
OTE
EEPROM M
: * Only the upper 8 bits in this word in EEPROM location are used and the lower 8 bits are ignored. The lower byte at
PCI Config space 0x08 is Device Revision and is read-only.
A
EEPROM Interface
Device Internal Register Sets
DDRESS
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
“Section 3.1, FIFO DATA LOADING AND UNLOADING IN 32-BIT FORMAT.” on page 28
EMORY
Special Register (Lower Word)
Special Register (Upper Word)
EEPROM D
Class Code (Continued)
Subsystem Vendor ID
Subsystem ID
Class Code
T
Vendor ID
Device ID
ABLE
ATA
4: EEPROM A
[D15:D0]
*
14
DDRESS
V258’
Table 5
16
PCI clocks from the rising edge of the PCI RST#
(WORD O
S
S
PACE
PCI C
D
below. Every time a read or write operation is
EFINITIONS
0x2C
0x00
0x02
0x08
0x0A
0x2E
0x48
0x4A
A
ONFIGURATION
DDRESS
FFSET
)
D
EFAULT
0x13A8
xr
0x0258
0x0200
0x0700
0x0000
0x0000
0x0000
0x0000
V
ALUES
REV. 1.0.0
.