xr17v258 Exar Corporation, xr17v258 Datasheet - Page 33

• Manufacturer Part Number: xr17v258
• Description: 66mhz Pci Bus Octal Uart With Power Management Support
• Manufacturer: Exar Corporation

xr
REV. 1.0.0
Automatic hardware or RTS/DTR and CTS/DSR flow control is used to prevent data overrun to the local
receiver FIFO and remote receiver FIFO. The RTS#/DTR# output pin is used to request remote unit to
suspend/restart data transmission while the CTS#/DSR# input pin is monitored to suspend/restart local
transmitter. The auto RTS/DTR and auto CTS/DSR flow control features are individually selected to fit specific
application requirement and enabled through EFR bit[7:6] and MCR bit [2] for either RTS/CTS or DTR/DSR
control signals. The auto RTS/DTR function must be started by asserting RTS/DTR# output pin (MCR bit [0] or
bit [1] to logic 1) after it is enabled.
Two interrupts associated with RTS/DTR and CTS/DSR flow control have been added to give indication when
RTS/DTR# pin or CTS/DSR# pin is de-asserted during operation. The RTS/DTR and CTS/DSR interrupts must
be first enabled by EFR bit [4], and then enabled individually by IER bits [7:6], and chosen with MCR bit [2].
Automatic hardware flow control is selected by setting bits [7 (CTS): 6 (RTS)] of the EFR register to logic 1. If
CTS# pin transitions from LOW to HIGH indicating a flow control request, ISR bit [5] will be set to logic 1, (if
enabled via IER bit [7:6]), and the UART will suspend TX transmissions as soon as the stop bit of the character
in process is shifted out. Transmission is resumed after the CTS# input returns to LOW, indicating more data
may be sent.
4.2
O
UTPUT
R
1000000
100000
153600
200000
225000
230400
250000
300000
400000
460800
500000
750000
921600
115200
EQUIRED
R
T
ATE
Automatic Hardware (RTS/CTS or DTR/DSR) Flow Control Operation
ABLE
D
ATA
12: T
YPICAL DATA RATES WITH A
D
16x Clock
(Decimal)
IVISOR FOR
13.0208
9.7656
6.6667
6.5104
3.2552
1.6276
3.75
7.5
1.5
15
6
5
3
2
66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT
O
Figure 12
BTAINABLE IN
D
9 12/16
6 11/16
3 12/16
1 10/16
7 8/16
6 8/16
3 4/16
1 8/16
V258
IVISOR
15
13
6
5
3
2
below explains how it works.
24 MH
DLM P
V
ALUE
Z CRYSTAL OR EXTERNAL CLOCK AT
33
ROGRAM
0
0
0
0
0
0
0
0
0
0
0
0
0
0
(HEX)
DLL P
V
ALUE
D
F
ROGRAM
9
7
6
6
6
5
3
3
3
2
1
1
(HEX)
DLD P
V
ALUE
ROGRAM
C
B
C
A
0
0
8
8
0
0
4
0
0
8
(HEX))
16X S
AMPLING
D
ATA
R
XR17V258
ATE
0.16
0.16
0.31
0.16
0.16
0.16
0
0
0
0
0
0
0
0
E
RROR
(%)