xr17v258 Exar Corporation, xr17v258 Datasheet - Page 28

• Manufacturer Part Number: xr17v258
• Description: 66mhz Pci Bus Octal Uart With Power Management Support
• Manufacturer: Exar Corporation

XR17V258
66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT
generators for standard or custom rates. Typically, the oscillator connections are shown in
further reading on oscillator circuit please see application note DAN108 on EXAR’s web site.
There are two methods to load transmit data and unload receive data from each UART channel. First, there is
a transmit data register and receive data register for each UART channel as shown in
programming. These registers support 8,
data transfer rate on the PCI bus. Additionally, a special register location provides receive data byte with its
associated error flags. This is a 16-bit or 32-bit read operation where the Line Status Register (LSR) content in
the UART channel register is paired along with the data byte. This operation further facilitates data unloading
with the error flags without having to read the LSR register separately. Furthermore, the XR17V258 supports
PCI burst mode for read/write operation of up to 64 bytes of data.
The second method is through each UART channel’s transmit holding register (THR) and receive holding
register (RHR). The THR and RHR registers are 16550 compatible so their access is limited to 8-bit format.
The software driver must separately read the LSR content for the associated error flags before reading the
data byte.
The XR17V258 supports PCI Burst Read and PCI Burst Write transactions anywhere in the mapped memory
region (except reserved areas). In addition, to utilize this feature fully, the device provides a separate memory
location (apart from the individual channel’s register set) where the RX and the TX FIFO can be read from/
written to, as shown in
support burst transactions:
For example, the locations for channel 2 are:
The RX FIFO data (up to the maximum 64 bytes) can be read out in a single burst 32-bit read operation
(maximum 16 DWORD reads) at memory locations 0x100 (channel 0), 0x300 (channel 1), 0x500
3.0 TRANSMIT AND RECEIVE DATA
3.1
3.1.1
FIFO DATA LOADING AND UNLOADING IN 32-BIT FORMAT.
Channel N: (for channels 0 through 7) where M = 2N + 1.
Channel 2:
Normal Rx FIFO Data Unloading at locations 0x100, 0x300, 0x500, 0x700
RX FIFO
TX FIFO
RX FIFO + status
RX FIFO
TX FIFO
RX FIFO + status
Table 5
F
IGURE
. The following is an extract from the table showing the memory locations that
10. T
:
:
:
:
:
:
YPICAL OSCILLATOR CONNECTIONS
22-47pF
16,
XTAL1
C1
24 and 32 bits wide format. In the 32-bit format, it increases the
R=300K to 400K
0xM00 - 0xM3F (64 bytes)
0xM00 - 0xM3F (64 bytes)
0xM80 - 0xMFF (64 bytes data + 64 bytes status)
0x500 - 0x53F (64 bytes)
0x500 - 0x53F (64 bytes)
0x580 - 0x5FF (64 bytes data + 64 bytes status)
14.7456
MHz
28
22-47pF
XTAL2
C2
Table 5
xr
Figure 10
set to ease
REV. 1.0.0
. For