xr17v258 Exar Corporation, xr17v258 Datasheet - Page 44

• Manufacturer Part Number: xr17v258
• Description: 66mhz Pci Bus Octal Uart With Power Management Support
• Manufacturer: Exar Corporation

XR17V258
66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT
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ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are
enabled.
ISR[5:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See
5.5.1, Interrupt Generation:” on page 44
5.5.1
5.5.2
P
LSR is by any of the LSR bits [4:1]. See IER bit [2] description on the previous page.
RXRDY is by RX trigger level.
RXRDY Time-out is by a 4-char plus 12 bits delay timer.
TXRDY is by TX trigger level or TX FIFO empty (or transmitter empty in auto RS-485 control).
MSR is by any of the MSR bits [3:0].
Receive Xoff/Special character is by detection of a Xoff or Special character.
CTS#/DSR# is when its transmitter toggles the input pin (from LOW to HIGH) during auto CTS/DSR flow
control enabled by EFR bit [7] and selection on MCR bit [2].
RTS#/DTR# is when its receiver toggles the output pin (from LOW to HIGH) during auto RTS/DTR flow
control enabled by EFR bit [6] and selection on MCR bit [2].
LSR interrupt is cleared by a read to the LSR register.
RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.
RXRDY Time-out interrupt is cleared by reading RHR.
TXRDY interrupt is cleared by a read to the ISR register or writing to THR.
MSR interrupt is cleared by a read to the MSR register.
Xoff interrupt is cleared by a read to ISR or when Xon character(s) is received.
Special character interrupt is cleared by a read to ISR or after the next character is received.
RTS#/DTR# and CTS#/DSR# status change interrupts are cleared by a read to the MSR register.
L
RIORITY
EVEL
X
1
2
3
4
5
6
7
Interrupt Generation:
Interrupt Clearing:
B
IT
0
0
0
0
0
0
1
0
[5]
B
IT
0
0
0
0
0
1
0
0
[4]
ISR R
B
IT
T
EGISTER
0
0
1
0
0
0
0
0
ABLE
[3]
B
15: I
S
IT
TATUS
1
1
1
0
0
0
0
0
[2]
NTERRUPT
and
B
B
ITS
IT
“Section 5.5.2, Interrupt Clearing:” on page 44
1
0
0
1
0
0
0
0
[1]
S
OURCE AND
44
B
IT
0
0
0
0
0
0
0
1
[0]
LSR (Receiver Line Status Register)
RXRDY (Received Data Ready)
RXRDY (Receive Data Time-out)
TXRDY (Transmitter Holding Register Empty)
MSR (Modem Status Register)
RXRDY (Received Xon/Xoff or Special character)
CTS#/DSR#, RTS#/DTR# change of state
None (default) or wake-up indicator
P
RIORITY
L
S
EVEL
OURCE OF THE INTERRUPT
Table 15
xr
). See
for details.
REV. 1.0.0
“Section