afs600 Actel Corporation, afs600 Datasheet - Page 138

• Manufacturer Part Number: afs600
• Description: Actel Fusion Programmable System Chips Mixed-signal Family With Optional Arm Support
• Manufacturer: Actel Corporation

Double Data Rate (DDR) Support
Fusion Pro I/Os support 350 MHz DDR inputs and
outputs. In DDR mode, new data is present on every
transition of the clock signal. Clock and data lines have
identical bandwidths and signal integrity requirements,
making it very efficient for implementing very high-
speed systems.
DDR interfaces can be implemented using HSTL, SSTL,
LVDS, and LVPECL I/O standards. In addition, high-speed
DDR interfaces can be implemented using LVDS I/O.
Input Support for DDR
The basic structure to support a DDR input is shown in
Figure
Figure 2-93 • DDR Input Register Support in Fusion Devices
2 -1 2 4
Actel Fusion Programmable System Chips
2-93. Three input registers are used to capture
Data
CLK
CLR
INBUF
INBUF
CLKBUF
A
B
C
A d v a n c e d v 1 . 4
DDR_IN
Input DDR
incoming data, which is presented to the core on each
rising edge of the I/O register clock.
Each I/O tile on Fusion devices supports DDR inputs.
Output Support for DDR
The basic DDR output structure is shown in
on page
every half clock cycle. Note: DDR macros and I/O registers
do not require additional routing. The combiner
automatically recognizes the DDR macro and pushes its
registers to the I/O register area at the edge of the chip.
The routing delay from the I/O registers to the I/O buffers
is already taken into account in the DDR macro.
Refer to the Actel application note
Devices
for more information.
FF1
FF2
2-125. New data is presented to the output
D
E
Out_QF
(to core)
Out_QR
(to core)
Using DDR for Fusion
Figure 2-94