afs600 Actel Corporation, afs600 Datasheet - Page 36

• Manufacturer Part Number: afs600
• Description: Actel Fusion Programmable System Chips Mixed-signal Family With Optional Arm Support
• Manufacturer: Actel Corporation

Clock Conditioning Circuits
In Fusion devices, the CCCs are used to implement
frequency division, frequency multiplication, phase
shifting, and delay operations.
The CCCs are available in six chip locations—each of the
four chip corners and the middle of the east and west
chip sides.
Each CCC can implement up to three independent global
buffers (with or without programmable delay), or a PLL
function (programmable frequency division/multiplication,
phase shift, and delays) with up to three global outputs.
Unused global outputs of a PLL can be used to
implement independent global buffers, up to a
maximum of three global outputs for a given CCC.
A global buffer can be placed in any of the three global
locations (CLKA-GLA, CLKB-GLB, and CLKC-GLC) of a
given CCC.
A PLL macro uses the CLKA CCC input to drive its reference
clock. It uses the GLA and, optionally, the GLB and GLC
global outputs to drive the global networks. A PLL macro
can also drive the YB and YC regular core outputs. The
GLB (or GLC) global output cannot be reused if the YB (or
YC) output is used
section on page 2-27
Notes:
1. Visit the
2. Many specific INBUF macros support the wide variety of single-ended and differential I/O standards for the Fusion family.
3. Refer to the
Figure 2-19 • Fusion CCC Options: Global Buffers with the PLL Macro
2 -2 2
Actel Fusion Programmable System Chips
page 2-27
Actel website
for signal descriptions.
Fusion, IGLOO/e, and ProASIC3/E Macro Library Guide
PADN
PADP
(Figure
Input LVDS/LVPECL Macro
PAD
for more information.
for future application notes concerning dynamic PLL reconfiguration. Refer to the
Clock Source
INBUF
2-19). Refer to the
2
Macro
Y
Y
"PLL Macro"
CLKA
EXTFB
POWERDOWN
OADIVRST
OADIVHALF
OADIV[4:0]
OAMUX[2:0]
DLYGLA[4:0]
OBDIV[4:0]
OBMUX[2:0]
DLYYB[4:0]
DLYGLB[4:0]
OCDIV[4:0]
OCMUX[2:0]
DLYYC[4:0]
DLYGLC[4:0]
FINDIV[6:0]
FBDIV[6:0]
FBDLY[4:0]
FBSEL[1:0]
XDLYSEL
VCOSEL[2:0]
Clock Conditioning
A d v a n c e d v 1 . 4
Each global buffer, as well as the PLL reference clock, can
be driven from one of the following:
The CCC block is fully configurable, either via flash
configuration bits set in the programming bitstream or
through an asynchronous interface. This asynchronous
interface is dynamically accessible from inside the Fusion
device to permit changes of parameters (such as divide
ratios) during device operation. To increase the
versatility and flexibility of the clock conditioning
system, the CCC configuration is determined either by
the user during the design process, with configuration
data being stored in flash memory as part of the device
programming procedure, or by writing data into a
dedicated shift register during normal device operation.
This latter mode allows the user to dynamically
reconfigure the CCC without the need for core
programming. The shift register is accessed through a
simple serial interface. Refer to the
in Actel’s Low-Power Flash Devices
and the
page 2-28
for more information.
LOCK
GLA
GLB
GLC
YB
YC
• 3 dedicated single-ended I/Os using a hardwired
• 2 dedicated differential I/Os using a hardwired
• The FPGA core
connection
connection
for more information.
"CCC and PLL Characteristics" section on
GLA
or
GLA and (GLB or YB)
or
GLA and (GLC or YC)
or
GLA and (GLB or YB) and
(GLC or YC)
Output
"PLL Macro" section on
UJTAG Applications
handbook chapter