afs600 Actel Corporation, afs600 Datasheet - Page 8

• Manufacturer Part Number: afs600
• Description: Actel Fusion Programmable System Chips Mixed-signal Family With Optional Arm Support
• Manufacturer: Actel Corporation

The Actel Fusion family offers revolutionary features,
never before available in an FPGA. The nonvolatile flash
technology gives the Fusion family the advantage of
being a secure, low-power, single-chip solution that is
live at power-up. Fusion is reprogrammable and offers
time to market benefits at an ASIC-level unit cost. These
features enable designers to create high-density systems
using existing ASIC or FPGA design flows and tools.
The family has up to 1.5 M system gates, supported with
up to 270 kbits of true dual-port SRAM, up to 8 Mbits of
flash memory, 1 kbit of user FlashROM, and up to 278
user I/Os. With integrated flash memory, the Fusion
family is the ultimate soft-processor platform. The
AFS600 and AFS1500 devices both support the Actel
ARM7 core (CoreMP7). The ARM-enabled versions are
identified with the M7 prefix as M7AFS600 and
M7AFS1500. The AFS250, AFS600, and AFS1500 devices
support the Actel Cortex-M1 core. The Cortex-M1-
enabled versions are identified with the M1 prefix as
M1AFS250, M1AFS600, and M1AFS1500.
Flash Advantages
Reduced Cost of Ownership
Advantages to the designer extend beyond low unit cost,
high performance, and ease of use. Flash-based Fusion
devices are live at power-up and do not need to be
loaded from an external boot PROM. On-board security
mechanisms
information and enable secure remote updates of the
FPGA logic. Designers can perform secure remote in-
system
iterations and field upgrades, with confidence that
valuable IP cannot be compromised or copied. Secure ISP
can be performed using the industry-standard AES
algorithm with MAC data authentication on the device.
The Fusion family device architecture mitigates the need
for ASIC migration at higher user volumes. This makes
the Fusion family a cost-effective ASIC replacement
solution for applications in the consumer, networking
and communications, computing, and avionics markets.
Security
As the nonvolatile, flash-based Fusion family requires no
boot PROM, there is no vulnerable external bitstream.
Fusion devices incorporate FlashLock, which provides a
unique combination of reprogrammability and design
security without external overhead, advantages that
only an FPGA with nonvolatile flash programming can
offer.
Fusion devices utilize a 128-bit flash-based key lock and a
separate AES key to secure programmed IP and
configuration data. The FlashROM data in Fusion devices
can also be encrypted prior to loading. Additionally, the
Flash memory blocks can be programmed during runtime
using
1 -2
Actel Fusion Programmable System Chips
the
reprogramming
industry-leading
prevent
access
to
support
AES-128
to
the
future
block
programming
design
cipher
A d v a n c e d v 1 .4
encryption standard (FIPS Publication 192). The AES
standard was adopted by the National Institute of
Standards and Technology (NIST) in 2000 and replaces
the DES standard, which was adopted in 1977. Fusion
devices have a built-in AES decryption engine and a
flash-based AES key that make Fusion devices the most
comprehensive programmable logic device security
solution available today. Fusion devices with AES-based
security allow for secure remote field updates over
public networks, such as the Internet, and ensure that
valuable IP remains out of the hands of system
overbuilders, system cloners, and IP thieves. As an
additional security measure, the FPGA configuration
data of a programmed Fusion device cannot be read
back, although secure design verification is possible.
During design, the user controls and defines both
internal and external access to the flash memory blocks.
Security, built into the FPGA fabric, is an inherent
component of the Fusion family. The Flash cells are
located beneath seven metal layers, and many device
design and layout techniques have been used to make
invasive attacks extremely difficult. Fusion with FlashLock
and AES security is unique in being highly resistant to
both invasive and noninvasive attacks. Your valuable IP is
protected, making secure remote ISP possible. A Fusion
device provides the most impenetrable security for
programmable logic designs.
Single Chip
Flash-based FPGAs store their configuration information
in
configuration data is an inherent part of the FPGA
structure, and no external configuration data needs to
be loaded at system power-up (unlike SRAM-based
FPGAs). Therefore, flash-based Fusion FPGAs do not
require system configuration components such as
EEPROMs
configuration data. This reduces bill-of-materials costs
and PCB area, and increases security and system
reliability.
Live at Power-Up
Flash-based Fusion devices are Level 0 live at power-up
(LAPU). LAPU Fusion devices greatly simplify total system
design and reduce total system cost by eliminating the
need for CPLDs. The Fusion LAPU clocking (PLLs) replaces
off-chip clocking resources. The Fusion mix of LAPU
clocking and analog resources makes these devices an
excellent choice for both system supervisor and system
management functions. LAPU from a single 3.3 V source
enables Fusion devices to initiate, control, and monitor
multiple voltage supplies while also providing system
clocks. In addition, glitches and brownouts in system
power will not corrupt the Fusion device flash
configuration. Unlike SRAM-based FPGAs, the device will
not have to be reloaded when system power is restored.
This enables reduction or complete removal of expensive
on-chip
or
flash
microcontrollers
cells.
Once
programmed,
to
load
device
the