afs600 Actel Corporation, afs600 Datasheet - Page 42

• Manufacturer Part Number: afs600
• Description: Actel Fusion Programmable System Chips Mixed-signal Family With Optional Arm Support
• Manufacturer: Actel Corporation

CCC and PLL Characteristics
Timing Characteristics
Table 2-13 • Fusion CCC/PLL Specification
2 -2 8
Parameter
Clock Conditioning Circuitry Input Frequency f
Clock Conditioning Circuitry Output Frequency f
Delay Increments in Programmable Delay Blocks
Number of Programmable Values in Each Programmable Delay Block
Input Period Jitter
CCC Output Peak-to-Peak Period Jitter F
Acquisition Time
Tracking Jitter
Output Duty Cycle
Delay Range in Block: Programmable Delay 1
Delay Range in Block: Programmable Delay 2
Delay Range in Block: Fixed Delay
Notes:
1. This delay is a function of voltage and temperature. See
2. T
3. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to PLL input clock edge. Tracking jitter
Actel Fusion Programmable System Chips
0.75 MHz to 24 MHz
24 MHz to 100 MHz
100 MHz to 250 MHz
250 MHz to 350 MHz
does not measure the variation in PLL output period, which is covered by period jitter parameter.
J
= 25°C, V
3
CC
= 1.5 V
1, 2
CCC_OUT
1, 2
1, 2
IN_CCC
1, 2
OUT_CCC
LockControl = 0
LockControl = 1
LockControl = 0
LockControl = 1
A d v a n c e d v 1 . 4
Table 3-7 on page 3-9
Network Used
1 Global
1.00%
1.50%
2.25%
3.50%
0.025
Min.
0.75
48.5
1.5
0.6
Max Peak-to-Peak Period Jitter
for deratings.
Typ.
160
2.2
Networks Used
3 Global
1.00%
2.25%
3.50%
1.50%
Max.
51.5
5.56
5.56
350
350
300
1.5
6.0
1.6
0.8
32
Unit
MHz
MHz
ms
%
ps
ns
µs
ns
ns
ns
ns
ns