afs600 Actel Corporation, afs600 Datasheet - Page 86

• Manufacturer Part Number: afs600
• Description: Actel Fusion Programmable System Chips Mixed-signal Family With Optional Arm Support
• Manufacturer: Actel Corporation

Analog Block
With the Fusion family, Actel has introduced the world's
first mixed-mode FPGA solution. Supporting a robust
analog peripheral mix, Fusion devices will support a wide
variety of applications. It is this Analog Block that
separates Fusion from all other FPGA solutions on the
market today.
By combining both flash and high-speed CMOS processes
in a single chip, these devices offer the best of both
worlds. The high-performance CMOS is used for building
RAM resources. These high-performance structures
support device operation up to 350 MHz. Additionally,
the advanced Actel 0.13 µm flash process incorporates
high-voltage transistors and a high-isolation, triple-well
process. Both of these are suited for the flash-based
programmable logic and nonvolatile memory structures.
High-voltage transistors support the integration of
analog technology in several ways. They aid in noise
immunity so that the analog portions of the chip can be
better isolated from the digital portions, increasing
analog accuracy. Because they support high voltages,
Actel flash FPGAs can be connected directly to high-
voltage input signals, eliminating the need for external
resistor divider networks, reducing component count,
and increasing accuracy. By supporting higher internal
voltages, the Actel advanced flash process enables high
dynamic range on analog circuitry, increasing precision
and signal–noise ratio. Actel flash FPGAs also drive high-
voltage outputs, eliminating the need for external level
shifters and drivers.
The unique triple-well process enables the integration of
high-performance analog features with increased noise
immunity and better isolation. By increasing the
efficiency of analog design, the triple-well process also
enables a smaller overall design size, reducing die size
and cost.
The Analog Block consists of the Analog Quad I/O
structure, RTC (for details refer to the
System" section on page
these elements are combined in the single Analog Block
macro, with which the user implements this functionality
(Figure
The Analog Block needs to be reset/reinitialized after the
core powers up or the device is programmed. An external
reset/initialize signal, which can come from the internal
voltage regulator when it powers up, must be applied.
2 -7 2
Actel Fusion Programmable System Chips
2-64).
2-31), ADC, and ACM. All of
"Real-Time Counter
A d v a n c e d v 1 . 4
Figure 2-64 • Analog Block Macro
VAREF
GNDREF
AV0
AC0
AT0
AV9
AC9
AT9
ATRETURN01
ATRETURN9
DENAV0
DENAC0
DENAT0
DENAV0
DENAC0
DENAT0
CMSTB0
CSMTB9
GDON0
GDON9
TMSTB0
TMSTB9
MODE[3:0]
TVC[7:0]
STC[7:0]
CHNUMBER[4:0]
TMSTINT
ADCSTART
VAREFSEL
PWRDWN
ADCRESET
RTCCLK
SYSCLK
ACMWEN
ACMRESET
ACMWDATA
ACMADDR
ACMCLK
AB
ACMRDATA[7:0]
RTCPSMMATCH
RTCXTLMODE
RESULT[11:0]
DATAVALID
RTCMATCH
CALIBRATE
RTCXTLSEL
DAVOUT0
DACOUT0
DAVOUT9
DACOUT9
DATOUT0
DATOUT9
SAMPLE
BUSY
AG0
AG1
AG9