afs600 Actel Corporation, afs600 Datasheet - Page 291

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afs600

Manufacturer Part Number
afs600
Description
Actel Fusion Programmable System Chips Mixed-signal Family With Optional Arm Support
Manufacturer
Actel Corporation
Datasheet

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Previous Version Changes in Current Version (A dv anced v 1. 4 )
(October 2006)
Advanced v0.7
Advanced v0.6
Advanced v0.5
(June 2006)
(continued)
The
The AFS090 and AFS250 devices were updated in the
The AFS250 device was updated in the
The AFS600 device was updated in the
The AFS090, AFS250, AFS600, and AFS1500 devices were updated in the
The AFS600 and AFS1500 devices were updated in the
The AFS600 device was updated in the
The AFS1500-FG484 and AFS1500-FG676 user I/O counts were updated in the
Single-/Double-Ended (Analog)"
The second paragraph of the
POWERDOWN.
The description for bit 0 was updated in
3.9 was changed to 7.8 in the
All function descriptions in
In
The
The
Table 2-35 • FIFO
The VAREF function description was updated in
The
mode.
The text in the
The
The
"All results are MSB justified in the ADC."
The information about the ADCSTART signal was updated in the
Table 2-46 • Analog Channel Specifications
Table 2-47 • ADC Characteristics in Direct Input Mode
Table 2-51 • ACM Address Decode Table for Analog Quad
In
Byte 3 was updated.
The
In
following features:
The
The
high current draw.
Table 2-19 • Flash Memory Block Pin
Table 2-53 • Analog Quad ACM Byte
Table 2-69 • Fusion Pro I/O
Single-ended receiver
Voltage-referenced differential receiver
LVDS/LVPECL differential receiver features
AFS090"108-Pin QFN" table
"RESET"
"RESET"
"Gate Driver"
"Analog-to-Digital Converter Block"
"Introduction"
"User I/O Naming Convention"
"V
"Voltage Monitor"
CC33PMP
was updated.
was updated.
"Current Monitor"
Analog Power Supply (3.3 V)"
was updated.
was updated to include information about forcing 1 V on the drain.
was updated to include information about digital inputs, outputs, and bibufs.
was updated to include information about low power mode and sleep
Table 2-18 • Signals for VRPSM
"Crystal Oscillator (Xtal
Features, the programmable delay descriptions were updated for the
table.
was updated.
was changed from 2 mV to 1 mV.
"PLL Macro"
was updated to include "V" and "z" descriptions
A d v an c ed v1 . 4
"208-Pin PQFP"
"208-Pin PQFP"
"676-Pin FBGA"
Table 2-17 • RTC Control/Status
Names, the RD[31:0] description was updated.
was updated with the following statement:
Assignment, the Function and Default Setting for Bit 6 in
was updated.
was updated to include information about avoiding
Table 2-36 • Analog Block Pin
was updated to include information about
"108-Pin QFN"
Osc)".
"484-Pin FBGA"
was updated.
table.
table.
table.
was updated.
Macro.
"ADC
Actel Fusion Programmable System Chips
table.
Description".
table.
"256-Pin FBGA"
Register.
Description.
"Package I/Os:
table.
2-102
2-105
2-111
2-114
2-117
2-121
2-142
2-203
Page
2-35.
4-12
4-20
4-28
2-27
2-34
2-36
2-38
2-55
2-57
2-71
2-73
2-77
2-81
2-84
2-89
2-92
4-2
4-2
4-8
4-8
iii
5-7

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