afs600 Actel Corporation, afs600 Datasheet - Page 39

• Manufacturer Part Number: afs600
• Description: Actel Fusion Programmable System Chips Mixed-signal Family With Optional Arm Support
• Manufacturer: Actel Corporation

Global Input Selections
Each global buffer, as well as the PLL reference clock, can be driven from one of the following
Notes:
1. Represents the global input pins. Globals have direct access to the clock conditioning block and are not routed via the FPGA fabric.
2. Instantiate the routed clock source input as follows:
3. LVDS-based clock sources are available in the east and west banks on all Fusion devices.
Figure 2-22 • Clock Input Sources Including CLKBUF, CLKBUF_LVDS/LVPECL, and CLKINT
• 3 dedicated single-ended I/Os using a hardwired connection
• 2 dedicated differential I/Os using a hardwired connection
• The FPGA core
Refer to the
a) Connect the output of a logic element to the clock input of the PLL, CLKDLY, or CLKINT macro.
b) Do not place a clock source I/O (INBUF or INBUF_LVPECL/LVDS) in a relevant global pin location.
Each shaded box represents an
input buffer called out by the
appropriate name: INBUF or
INBUF_LVDS/LVPECL.
Sample Pin Names
"User I/O Naming Convention" section on page 2-142
GAA[0:2]: GA represents global in the northwest corner
of the device. A[0:2]: designates specific A clock source.
GAA0
GAA1
GAA2
1
1
1
+
+
A d v an c ed v1 . 4
To Core
for more information.
(from FPGA core)
Routed Clock
Actel Fusion Programmable System Chips
Source for CCC
(CLKA or CLKB or CLKC)
2
(Figure
2-22):
2-25